4 files changed, 262 insertions, 21 deletions
diff --git a/src/arm32/instruction/display.rs b/src/arm32/instruction/display.rs
index d3e359a..9193edb 100644
--- a/src/arm32/instruction/display.rs
+++ b/src/arm32/instruction/display.rs
@@ -1,4 +1,4 @@
-// Copyright 2021-2024 Gabriel Bjørnager Jensen.
+// Copyright 2024 Gabriel Bjørnager Jensen.
 //
 // This file is part of Pollex.
 //
@@ -28,13 +28,29 @@ impl Display for Instruction {
 use Instruction::*;
 
 match *self {
- Branch { condition, immediate } => {
- write!(f, "B{condition} <#{immediate}>")
- },
+ Add { predicate, destination, base, source, s }
+ => write!(f, "ADD{predicate}{s} {destination}, {base}, {source}"),
 
- BranchLink { condition, immediate } => {
- write!(f, "BL{condition} <#{immediate}>")
- },
+ Branch { predicate, immediate }
+ => write!(f, "B{predicate} <{immediate}>"),
+
+ BranchExchange { predicate, register }
+ => write!(f, "BX{predicate} {register}"),
+
+ BranchLink { predicate, immediate }
+ => write!(f, "BL{predicate} <{immediate}>"),
+
+ Breakpoint { immediate }
+ => write!(f, "BKPT {immediate}"),
+
+ Move { predicate, destination, source, s }
+ => write!(f, "MOV{predicate}{s} {destination}, {source}"),
+
+ MoveNegated { predicate, destination, source, s }
+ => write!(f, "MVN{predicate}{s} {destination}, {source}"),
+
+ SoftwareInterrupt { predicate, immediate }
+ => write!(f, "SWI{predicate} {immediate}"),
 }
 }
 }
diff --git a/src/arm32/instruction/encode_arm.rs b/src/arm32/instruction/encode_arm.rs
new file mode 100644
index 0000000..a24ec28
--- /dev/null
+++ b/src/arm32/instruction/encode_arm.rs
@@ -0,0 +1,130 @@
+// Copyright 2024 Gabriel Bjørnager Jensen.
+//
+// This file is part of Pollex.
+//
+// Pollex is free software: you can redistribute it
+// and/or modify it under the terms of the GNU Af-
+// fero General Public License as published by the
+// Free Software Foundation, either version 3 of
+// the License, or (at your option) any later ver-
+// sion.
+//
+// Pollex is distributed in the hope that it will
+// be useful, but WITHOUT ANY WARRANTY; without
+// even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+// Affero General Public License for more details.
+//
+// You should have received a copy of the GNU Af-
+// fero General Public License along with Pollex.
+// If not, see <https://www.gnu.org/licenses/>.
+
+use crate::Result;
+use crate::arm32::{ArmOpcode, Instruction, Shifter};
+
+impl Instruction {
+ pub fn encode_arm(&self) -> Result<ArmOpcode> {
+ use Instruction::*;
+
+ let mut opcode = 0b00000000_00000000_00000000_00000000;
+
+ match *self {
+ Branch { predicate, .. } => {
+ opcode |= 0b00001011_00000000_00000000_00000000;
+ opcode |= (predicate as u32) << 0x1C;
+ },
+
+ BranchLink { predicate, .. } => {
+ opcode |= 0b00001010_00000000_00000000_00000000;
+ opcode |= (predicate as u32) << 0x1C;
+ //opcode |= immediate.to_bits::<0x18>() >> 0x8
+ },
+
+ Breakpoint { immediate } => {
+ opcode |= 0b11100001_00100000_00000000_01110000;
+ opcode |= immediate.get() & 0b00000000_00000000_00000000_00001111;
+ opcode |= (immediate.get() & 0b00000000_00000000_11111111_11110000) << 0x4;
+ },
+
+ Move { predicate, destination, source, s } => {
+ opcode |= 0b00000001_10100000_00000000_00000000;
+ opcode |= (destination as u32) << 0xC;
+ opcode |= u32::from(s.is_on()) << 0x14;
+ opcode |= (predicate as u32) << 0x1C;
+
+ opcode = add_shifter(opcode, source);
+ },
+
+ SoftwareInterrupt { predicate, immediate } => {
+ opcode |= 0b00001111_00000000_00000000_00000000;
+ opcode |= immediate.get() & 0b00000000_11111111_11111111_11111111;
+ opcode |= (predicate as u32) << 0x1C;
+ },
+
+ _ => todo!(),
+ }
+
+ Ok(ArmOpcode::from_u32(opcode))
+ }
+}
+
+fn add_shifter(mut opcode: u32, shifter: Shifter) -> u32 {
+ match shifter {
+ | Shifter::ArithmeticShiftRightImmediate { source, shift }
+ | Shifter::LogicalShiftLeftImmediate { source, shift }
+ | Shifter::LogicalShiftRightImmediate { source, shift }
+ | Shifter::RotateRightImmediate { source, shift }
+ => {
+ let code = match shifter {
+ Shifter::LogicalShiftLeftImmediate { .. } => 0b00,
+ Shifter::LogicalShiftRightImmediate { .. } => 0b01,
+ Shifter::ArithmeticShiftRightImmediate { .. } => 0b10,
+ Shifter::RotateRightImmediate { .. } => 0b11,
+
+ _ => unreachable!(),
+ };
+
+ opcode |= source as u32;
+ opcode |= code << 0x5;
+ opcode |= shift.get() << 0x7;
+ },
+
+ Shifter::RotateRightExtend { .. } => {
+ todo!()
+ },
+
+ | Shifter::ArithmeticShiftRightRegister { source, .. }
+ | Shifter::LogicalShiftLeftRegister { source, .. }
+ | Shifter::LogicalShiftRightRegister { source, .. }
+ | Shifter::RotateRightRegister { source, .. }
+ => {
+ let _code = match shifter {
+ Shifter::LogicalShiftLeftRegister { .. } => 0b00,
+ Shifter::LogicalShiftRightRegister { .. } => 0b01,
+ Shifter::ArithmeticShiftRightRegister { .. } => 0b10,
+ Shifter::RotateRightRegister { .. } => 0b11,
+
+ _ => unreachable!(),
+ };
+
+ opcode |= 0b00000000_00000000_00000000_00010000;
+ opcode |= source as u32;
+ },
+
+ Shifter::Immediate { immediate } => {
+ let (immediate, rotate) = if immediate <= 0xFF {
+ let immediate = immediate.get();
+
+ (immediate, 0x00)
+ } else {
+ todo!()
+ };
+
+ opcode |= 0b00000010_00000000_00000000_00000000;
+ opcode |= immediate;
+ opcode |= rotate << 0x8;
+ },
+ }
+
+ opcode
+}
diff --git a/src/arm32/instruction/mod.rs b/src/arm32/instruction/mod.rs
index 1e1971d..8e527d5 100644
--- a/src/arm32/instruction/mod.rs
+++ b/src/arm32/instruction/mod.rs
@@ -1,4 +1,4 @@
-// Copyright 2021-2024 Gabriel Bjørnager Jensen.
+// Copyright 2024 Gabriel Bjørnager Jensen.
 //
 // This file is part of Pollex.
 //
@@ -23,12 +23,56 @@
 mod test;
 
 mod display;
+mod encode_arm;
 
-use crate::arm32::Condition;
+use crate::arm32::{
+ Predicate,
+ Flag,
+ Register,
+ Shifter,
+ Signed,
+ Unsigned,
+};
 
 /// An Arm32 instruction.
+#[derive(Clone, Debug, Eq, PartialEq)]
 pub enum Instruction {
- Branch { condition: Condition, immediate: i32 },
+ Add {
+ predicate: Predicate,
+ destination: Register,
+ base: Register,
+ source: Shifter,
+ s: Flag<'S'> },
 
- BranchLink { condition: Condition, immediate: i32 },
+ Branch {
+ predicate: Predicate,
+ immediate: Signed },
+
+ BranchExchange {
+ predicate: Predicate,
+ register: Register },
+
+ BranchLink {
+ predicate: Predicate,
+ immediate: Signed
+ },
+
+ Breakpoint {
+ immediate: Unsigned },
+
+ Move {
+ predicate: Predicate,
+ destination: Register,
+ source: Shifter,
+ s: Flag<'S'> },
+
+ MoveNegated {
+ predicate: Predicate,
+ destination: Register,
+ source: Shifter,
+ s: Flag<'S'> },
+
+ SoftwareInterrupt {
+ predicate: Predicate,
+ immediate: Unsigned },
 }
diff --git a/src/arm32/instruction/test.rs b/src/arm32/instruction/test.rs
index 5c8d523..6977d46 100644
--- a/src/arm32/instruction/test.rs
+++ b/src/arm32/instruction/test.rs
@@ -1,4 +1,4 @@
-// Copyright 2021-2024 Gabriel Bjørnager Jensen.
+// Copyright 2024 Gabriel Bjørnager Jensen.
 //
 // This file is part of Pollex.
 //
@@ -19,21 +19,72 @@
 // fero General Public License along with Pollex.
 // If not, see <https://www.gnu.org/licenses/>.
 
-use crate::arm32::{Condition, Instruction};
+use crate::arm32::{
+ Predicate,
+ Flag,
+ Instruction,
+ Register,
+ Shifter,
+ Signed,
+ Unsigned,
+};
 
 use alloc::format;
+use alloc::vec::Vec;
 
 #[test]
 fn test_arm32_instruction() {
- let assert_display = |instruction: Instruction, display: &str| {
- assert_eq!(format!("{instruction}"), display);
- };
-
- assert_display(
+ let tree = [
 Instruction::BranchLink {
- condition: Condition::HigherOrSame,
- immediate: 0xF,
+ predicate: Predicate::HigherOrSame,
+ immediate: Signed::new(0x1F),
+ },
+
+ Instruction::Breakpoint {
+ immediate: Unsigned::new(0x45),
+ },
+
+ Instruction::SoftwareInterrupt {
+ predicate: Predicate::Always,
+ immediate: Unsigned::new(0x54),
+ },
+
+ Instruction::Move {
+ predicate: Predicate::Plus,
+ destination: Register::Pc,
+ source: Shifter::ArithmeticShiftRightImmediate { source: Register::R3, shift: Unsigned::new(0x20) },
+ s: Flag::On,
 },
- "BLHS <#15>",
+ ];
+
+ let mut displays = Vec::with_capacity(tree.len());
+ let mut opcodes = Vec::with_capacity(tree.len());
+
+ for instruction in tree {
+ displays.push(format!("{instruction}"));
+ opcodes.push(instruction.encode_arm().unwrap());
+ }
+
+ assert_eq!(
+ displays,
+ [
+ "BLHS <#+31>",
+ "BKPT #69",
+ "SWI #84",
+ "MOVPLS pc, r3, ASR #32",
+ ],
 );
+
+ assert_eq!(
+ opcodes,
+ [
+ 0b00101010_00000000_00000000_00000000,
+ 0b11100001_00100000_00000100_01110101,
+ 0b11101111_00000000_00000000_01010100,
+ 0b01010001_10110000_11110000_01000011,
+ ],
+ )
 }
+
+// 01010001101100001111000001000011
+// 01010001101100001111000001000011