diff options
| -rw-r--r-- | CHANGELOG.md | 16 | ||||
| -rw-r--r-- | Cargo.toml | 2 | ||||
| -rw-r--r-- | README.md | 4 | ||||
| -rw-r--r-- | src/arch/mod.rs | 9 | ||||
| -rw-r--r-- | src/arm32/arm_opcode/mod.rs | 58 | ||||
| -rw-r--r-- | src/arm32/flag/mod.rs | 50 | ||||
| -rw-r--r-- | src/arm32/instruction/display.rs | 30 | ||||
| -rw-r--r-- | src/arm32/instruction/encode_arm.rs | 130 | ||||
| -rw-r--r-- | src/arm32/instruction/mod.rs | 52 | ||||
| -rw-r--r-- | src/arm32/instruction/test.rs | 71 | ||||
| -rw-r--r-- | src/arm32/mod.rs | 11 | ||||
| -rw-r--r-- | src/arm32/predicate/mod.rs (renamed from src/arm32/condition/mod.rs) | 18 | ||||
| -rw-r--r-- | src/arm32/register/mod.rs | 7 | ||||
| -rw-r--r-- | src/arm32/shifter/mod.rs (renamed from src/arm32/address/mod.rs) | 35 | ||||
| -rw-r--r-- | src/arm32/signed/mod.rs | 128 | ||||
| -rw-r--r-- | src/arm32/thumb_opcode/mod.rs | 58 | ||||
| -rw-r--r-- | src/arm32/unsigned/mod.rs | 134 | ||||
| -rw-r--r-- | src/error/mod.rs | 49 | ||||
| -rw-r--r-- | src/lib.rs | 5 |
19 files changed, 807 insertions, 60 deletions
diff --git a/CHANGELOG.md b/CHANGELOG.md index 867bfbc..c070b0d 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -3,6 +3,22 @@ This is the changelog of Pollex. See `"README.md"` for more information. +## 0.2.0 + +* Bump minor +* Update copyright years +* Add new Arm32 instructions: `SoftwareInterrupt`, `Move`, `BranchExchange`, `Breakpoint`, `MoveNegated`, `Add` +* Derive more +* Add `arm32::Flag`, `arm32::Unsigned`, and `arm32::Signed` types +* Add instruction encoder (currently only for Arm) +* Add `arm32::ArmOpcode` and `arm32::ThumbOpcode` types +* Rename `arm32::Address` to `arm32::Shifter` +* Add `Error` type +* Rework instructions +* Update readme +* Rename `arm32::Condition` to `arm32::Predicate` +* Update documentation + ## 0.1.2 * Update project description @@ -1,6 +1,6 @@ [package] name = "pollex" -version = "0.1.2" +version = "0.2.0" authors = ["Gabriel Bjørnager Jensen"] edition = "2021" description = "Arm instruction manipulator." @@ -6,7 +6,7 @@ See [Docs.rs](https://docs.rs/pollex/) for documentation. ## Copyright & Licensing -Copyright 2021-2024 Gabriel Bjørnager Jensen. +Copyright 2024 Gabriel Bjørnager Jensen. This program is free software: you can redistribute it and/or modify it under the terms of the GNU Affero General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. @@ -16,4 +16,4 @@ You should have received a copy of the GNU Affero General Public License along w ## Trademarks -Arm is a registered trademark of Arm Limited (or its subsidiaries or affiliates). +Arm and Thumb are registered trademarks or trademarks of Arm Limited (or its subsidiaries or affiliates). diff --git a/src/arch/mod.rs b/src/arch/mod.rs index 2df0176..8a28b67 100644 --- a/src/arch/mod.rs +++ b/src/arch/mod.rs @@ -1,4 +1,4 @@ -// Copyright 2021-2024 Gabriel Bjørnager Jensen. +// Copyright 2024 Gabriel Bjørnager Jensen. // // This file is part of Pollex. // @@ -19,10 +19,9 @@ // fero General Public License along with Pollex. // If not, see <https://www.gnu.org/licenses/>. - +/// An Arm architecture. #[derive(Clone, Copy, Debug, Eq, Ord, PartialEq, PartialOrd)] -#[repr(u8)] pub enum Arch { - Arm32 = 0x00, - Arm64 = 0x01, + Arm32, + Arm64, } diff --git a/src/arm32/arm_opcode/mod.rs b/src/arm32/arm_opcode/mod.rs new file mode 100644 index 0000000..52f36aa --- /dev/null +++ b/src/arm32/arm_opcode/mod.rs @@ -0,0 +1,58 @@ +// Copyright 2024 Gabriel Bjørnager Jensen. +// +// This file is part of Pollex. +// +// Pollex is free software: you can redistribute it +// and/or modify it under the terms of the GNU Af- +// fero General Public License as published by the +// Free Software Foundation, either version 3 of +// the License, or (at your option) any later ver- +// sion. +// +// Pollex is distributed in the hope that it will +// be useful, but WITHOUT ANY WARRANTY; without +// even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// Affero General Public License for more details. +// +// You should have received a copy of the GNU Af- +// fero General Public License along with Pollex. +// If not, see <https://www.gnu.org/licenses/>. + +use core::fmt::{Debug, Display, Formatter}; + +/// An Arm opcode. +#[derive(Clone, Copy, Eq, PartialEq)] +#[repr(transparent)] +pub struct ArmOpcode(u32); + +impl ArmOpcode { + /// Creates a new opcode from a primitive. + #[inline(always)] + #[must_use] + pub const fn from_u32(value: u32) -> Self { Self(value.to_le()) } + + /// Extracts the opcode as a primitive. + #[inline(always)] + #[must_use] + pub const fn to_u32(self) -> u32 { self.0.to_le() } +} + +impl Debug for ArmOpcode { + #[inline(always)] + fn fmt(&self, f: &mut Formatter) -> core::fmt::Result { + write!(f, "{:032b}", self.to_u32()) + } +} + +impl Display for ArmOpcode { + #[inline(always)] + fn fmt(&self, f: &mut Formatter) -> core::fmt::Result { + write!(f, "{:#018X}", self.to_u32()) + } +} + +impl PartialEq<u32> for ArmOpcode { + #[inline(always)] + fn eq(&self, other: &u32) -> bool { self.0 == *other } +} diff --git a/src/arm32/flag/mod.rs b/src/arm32/flag/mod.rs new file mode 100644 index 0000000..33755b7 --- /dev/null +++ b/src/arm32/flag/mod.rs @@ -0,0 +1,50 @@ +// Copyright 2024 Gabriel Bjørnager Jensen. +// +// This file is part of Pollex. +// +// Pollex is free software: you can redistribute it +// and/or modify it under the terms of the GNU Af- +// fero General Public License as published by the +// Free Software Foundation, either version 3 of +// the License, or (at your option) any later ver- +// sion. +// +// Pollex is distributed in the hope that it will +// be useful, but WITHOUT ANY WARRANTY; without +// even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// Affero General Public License for more details. +// +// You should have received a copy of the GNU Af- +// fero General Public License along with Pollex. +// If not, see <https://www.gnu.org/licenses/>. + +use core::fmt::Display; + +/// A flag. +#[derive(Clone, Copy, Debug, Eq, PartialEq)] +#[repr(u8)] +pub enum Flag<const C: char> { + Off = 0x0, + On = 0x1, +} + +impl<const C: char> Flag<C> { + #[inline(always)] + #[must_use] + pub const fn is_off(self) -> bool { self as u8 == Self::Off as u8 } + + #[inline(always)] + #[must_use] + pub const fn is_on(self) -> bool { self as u8 == Self::On as u8 } +} + +impl<const C: char> Display for Flag<C> { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + if self.is_on() { + write!(f, "{C}")?; + } + + Ok(()) + } +} diff --git a/src/arm32/instruction/display.rs b/src/arm32/instruction/display.rs index d3e359a..9193edb 100644 --- a/src/arm32/instruction/display.rs +++ b/src/arm32/instruction/display.rs @@ -1,4 +1,4 @@ -// Copyright 2021-2024 Gabriel Bjørnager Jensen. +// Copyright 2024 Gabriel Bjørnager Jensen. // // This file is part of Pollex. // @@ -28,13 +28,29 @@ impl Display for Instruction { use Instruction::*; match *self { - Branch { condition, immediate } => { - write!(f, "B{condition} <#{immediate}>") - }, + Add { predicate, destination, base, source, s } + => write!(f, "ADD{predicate}{s} {destination}, {base}, {source}"), - BranchLink { condition, immediate } => { - write!(f, "BL{condition} <#{immediate}>") - }, + Branch { predicate, immediate } + => write!(f, "B{predicate} <{immediate}>"), + + BranchExchange { predicate, register } + => write!(f, "BX{predicate} {register}"), + + BranchLink { predicate, immediate } + => write!(f, "BL{predicate} <{immediate}>"), + + Breakpoint { immediate } + => write!(f, "BKPT {immediate}"), + + Move { predicate, destination, source, s } + => write!(f, "MOV{predicate}{s} {destination}, {source}"), + + MoveNegated { predicate, destination, source, s } + => write!(f, "MVN{predicate}{s} {destination}, {source}"), + + SoftwareInterrupt { predicate, immediate } + => write!(f, "SWI{predicate} {immediate}"), } } } diff --git a/src/arm32/instruction/encode_arm.rs b/src/arm32/instruction/encode_arm.rs new file mode 100644 index 0000000..a24ec28 --- /dev/null +++ b/src/arm32/instruction/encode_arm.rs @@ -0,0 +1,130 @@ +// Copyright 2024 Gabriel Bjørnager Jensen. +// +// This file is part of Pollex. +// +// Pollex is free software: you can redistribute it +// and/or modify it under the terms of the GNU Af- +// fero General Public License as published by the +// Free Software Foundation, either version 3 of +// the License, or (at your option) any later ver- +// sion. +// +// Pollex is distributed in the hope that it will +// be useful, but WITHOUT ANY WARRANTY; without +// even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// Affero General Public License for more details. +// +// You should have received a copy of the GNU Af- +// fero General Public License along with Pollex. +// If not, see <https://www.gnu.org/licenses/>. + +use crate::Result; +use crate::arm32::{ArmOpcode, Instruction, Shifter}; + +impl Instruction { + pub fn encode_arm(&self) -> Result<ArmOpcode> { + use Instruction::*; + + let mut opcode = 0b00000000_00000000_00000000_00000000; + + match *self { + Branch { predicate, .. } => { + opcode |= 0b00001011_00000000_00000000_00000000; + opcode |= (predicate as u32) << 0x1C; + }, + + BranchLink { predicate, .. } => { + opcode |= 0b00001010_00000000_00000000_00000000; + opcode |= (predicate as u32) << 0x1C; + //opcode |= immediate.to_bits::<0x18>() >> 0x8 + }, + + Breakpoint { immediate } => { + opcode |= 0b11100001_00100000_00000000_01110000; + opcode |= immediate.get() & 0b00000000_00000000_00000000_00001111; + opcode |= (immediate.get() & 0b00000000_00000000_11111111_11110000) << 0x4; + }, + + Move { predicate, destination, source, s } => { + opcode |= 0b00000001_10100000_00000000_00000000; + opcode |= (destination as u32) << 0xC; + opcode |= u32::from(s.is_on()) << 0x14; + opcode |= (predicate as u32) << 0x1C; + + opcode = add_shifter(opcode, source); + }, + + SoftwareInterrupt { predicate, immediate } => { + opcode |= 0b00001111_00000000_00000000_00000000; + opcode |= immediate.get() & 0b00000000_11111111_11111111_11111111; + opcode |= (predicate as u32) << 0x1C; + }, + + _ => todo!(), + } + + Ok(ArmOpcode::from_u32(opcode)) + } +} + +fn add_shifter(mut opcode: u32, shifter: Shifter) -> u32 { + match shifter { + | Shifter::ArithmeticShiftRightImmediate { source, shift } + | Shifter::LogicalShiftLeftImmediate { source, shift } + | Shifter::LogicalShiftRightImmediate { source, shift } + | Shifter::RotateRightImmediate { source, shift } + => { + let code = match shifter { + Shifter::LogicalShiftLeftImmediate { .. } => 0b00, + Shifter::LogicalShiftRightImmediate { .. } => 0b01, + Shifter::ArithmeticShiftRightImmediate { .. } => 0b10, + Shifter::RotateRightImmediate { .. } => 0b11, + + _ => unreachable!(), + }; + + opcode |= source as u32; + opcode |= code << 0x5; + opcode |= shift.get() << 0x7; + }, + + Shifter::RotateRightExtend { .. } => { + todo!() + }, + + | Shifter::ArithmeticShiftRightRegister { source, .. } + | Shifter::LogicalShiftLeftRegister { source, .. } + | Shifter::LogicalShiftRightRegister { source, .. } + | Shifter::RotateRightRegister { source, .. } + => { + let _code = match shifter { + Shifter::LogicalShiftLeftRegister { .. } => 0b00, + Shifter::LogicalShiftRightRegister { .. } => 0b01, + Shifter::ArithmeticShiftRightRegister { .. } => 0b10, + Shifter::RotateRightRegister { .. } => 0b11, + + _ => unreachable!(), + }; + + opcode |= 0b00000000_00000000_00000000_00010000; + opcode |= source as u32; + }, + + Shifter::Immediate { immediate } => { + let (immediate, rotate) = if immediate <= 0xFF { + let immediate = immediate.get(); + + (immediate, 0x00) + } else { + todo!() + }; + + opcode |= 0b00000010_00000000_00000000_00000000; + opcode |= immediate; + opcode |= rotate << 0x8; + }, + } + + opcode +} diff --git a/src/arm32/instruction/mod.rs b/src/arm32/instruction/mod.rs index 1e1971d..8e527d5 100644 --- a/src/arm32/instruction/mod.rs +++ b/src/arm32/instruction/mod.rs @@ -1,4 +1,4 @@ -// Copyright 2021-2024 Gabriel Bjørnager Jensen. +// Copyright 2024 Gabriel Bjørnager Jensen. // // This file is part of Pollex. // @@ -23,12 +23,56 @@ mod test; mod display; +mod encode_arm; -use crate::arm32::Condition; +use crate::arm32::{ + Predicate, + Flag, + Register, + Shifter, + Signed, + Unsigned, +}; /// An Arm32 instruction. +#[derive(Clone, Debug, Eq, PartialEq)] pub enum Instruction { - Branch { condition: Condition, immediate: i32 }, + Add { + predicate: Predicate, + destination: Register, + base: Register, + source: Shifter, + s: Flag<'S'> }, - BranchLink { condition: Condition, immediate: i32 }, + Branch { + predicate: Predicate, + immediate: Signed }, + + BranchExchange { + predicate: Predicate, + register: Register }, + + BranchLink { + predicate: Predicate, + immediate: Signed + }, + + Breakpoint { + immediate: Unsigned }, + + Move { + predicate: Predicate, + destination: Register, + source: Shifter, + s: Flag<'S'> }, + + MoveNegated { + predicate: Predicate, + destination: Register, + source: Shifter, + s: Flag<'S'> }, + + SoftwareInterrupt { + predicate: Predicate, + immediate: Unsigned }, } diff --git a/src/arm32/instruction/test.rs b/src/arm32/instruction/test.rs index 5c8d523..6977d46 100644 --- a/src/arm32/instruction/test.rs +++ b/src/arm32/instruction/test.rs @@ -1,4 +1,4 @@ -// Copyright 2021-2024 Gabriel Bjørnager Jensen. +// Copyright 2024 Gabriel Bjørnager Jensen. // // This file is part of Pollex. // @@ -19,21 +19,72 @@ // fero General Public License along with Pollex. // If not, see <https://www.gnu.org/licenses/>. -use crate::arm32::{Condition, Instruction}; +use crate::arm32::{ + Predicate, + Flag, + Instruction, + Register, + Shifter, + Signed, + Unsigned, +}; use alloc::format; +use alloc::vec::Vec; #[test] fn test_arm32_instruction() { - let assert_display = |instruction: Instruction, display: &str| { - assert_eq!(format!("{instruction}"), display); - }; - - assert_display( + let tree = [ Instruction::BranchLink { - condition: Condition::HigherOrSame, - immediate: 0xF, + predicate: Predicate::HigherOrSame, + immediate: Signed::new(0x1F), + }, + + Instruction::Breakpoint { + immediate: Unsigned::new(0x45), + }, + + Instruction::SoftwareInterrupt { + predicate: Predicate::Always, + immediate: Unsigned::new(0x54), + }, + + Instruction::Move { + predicate: Predicate::Plus, + destination: Register::Pc, + source: Shifter::ArithmeticShiftRightImmediate { source: Register::R3, shift: Unsigned::new(0x20) }, + s: Flag::On, }, - "BLHS <#15>", + ]; + + let mut displays = Vec::with_capacity(tree.len()); + let mut opcodes = Vec::with_capacity(tree.len()); + + for instruction in tree { + displays.push(format!("{instruction}")); + opcodes.push(instruction.encode_arm().unwrap()); + } + + assert_eq!( + displays, + [ + "BLHS <#+31>", + "BKPT #69", + "SWI #84", + "MOVPLS pc, r3, ASR #32", + ], ); + + assert_eq!( + opcodes, + [ + 0b00101010_00000000_00000000_00000000, + 0b11100001_00100000_00000100_01110101, + 0b11101111_00000000_00000000_01010100, + 0b01010001_10110000_11110000_01000011, + ], + ) } + +// 01010001101100001111000001000011 +// 01010001101100001111000001000011 diff --git a/src/arm32/mod.rs b/src/arm32/mod.rs index e73980a..bfc7a5d 100644 --- a/src/arm32/mod.rs +++ b/src/arm32/mod.rs @@ -1,4 +1,4 @@ -// Copyright 2021-2024 Gabriel Bjørnager Jensen. +// Copyright 2024 Gabriel Bjørnager Jensen. // // This file is part of Pollex. // @@ -24,7 +24,12 @@ //! This includes T variants of Arm32. use crate::use_mod; -use_mod!(pub address); -use_mod!(pub condition); +use_mod!(pub arm_opcode); +use_mod!(pub predicate); +use_mod!(pub flag); use_mod!(pub instruction); use_mod!(pub register); +use_mod!(pub shifter); +use_mod!(pub signed); +use_mod!(pub thumb_opcode); +use_mod!(pub unsigned); diff --git a/src/arm32/condition/mod.rs b/src/arm32/predicate/mod.rs index f8d81ba..0b761d9 100644 --- a/src/arm32/condition/mod.rs +++ b/src/arm32/predicate/mod.rs @@ -1,4 +1,4 @@ -// Copyright 2021-2024 Gabriel Bjørnager Jensen. +// Copyright 2024 Gabriel Bjørnager Jensen. // // This file is part of Pollex. // @@ -21,15 +21,15 @@ use core::fmt::Display; -/// A condition code. +/// An instruction predicate (condition code). /// -/// Most Arm32 instructions embed a condition code. +/// Most Arm32 opcodes embed a condition code, as well as some Thumb opcodes. /// -/// Any 4-bit values is always a valid condition code *except* `0b1111`, which sometimes denotes a different instruction altogether +/// Any 4-bit values is always a valid predicate *except* `0b1111`, which sometimes denotes a different instruction altogether /// In most cases, it is invalid, however.. -#[derive(Clone, Copy, Eq, Ord, PartialEq, PartialOrd)] +#[derive(Clone, Copy, Debug, Eq, Ord, PartialEq, PartialOrd)] #[repr(u8)] -pub enum Condition { +pub enum Predicate { Equal = 0b0000, NotEqual = 0b0001, HigherOrSame = 0b0010, @@ -48,9 +48,9 @@ pub enum Condition { //Never = 0b1111, } -impl Display for Condition { +impl Display for Predicate { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - use Condition::*; + use Predicate::*; match *self { Equal => write!(f, "EQ"), @@ -67,7 +67,7 @@ impl Display for Condition { LessThan => write!(f, "LT"), GreaterThan => write!(f, "GT"), LessThanOrEqual => write!(f, "LE"), - Always => write!(f, "AL"), + Always => Ok(()), // No need to print this one. //Never => write!(f, "NV"), } } diff --git a/src/arm32/register/mod.rs b/src/arm32/register/mod.rs index 366ab16..2df521b 100644 --- a/src/arm32/register/mod.rs +++ b/src/arm32/register/mod.rs @@ -1,4 +1,4 @@ -// Copyright 2021-2024 Gabriel Bjørnager Jensen. +// Copyright 2024 Gabriel Bjørnager Jensen. // // This file is part of Pollex. // @@ -23,8 +23,9 @@ use core::fmt::Display; /// An Arm register. /// -/// Registers are number `R<N>`, where *N* denotes a decimal number from (0) to (15). -/// Some registers have aliases, such as `r15|pc`. +/// Some opcodes can only encode specific registers. +/// For example, many Thumb instructions only accept registers from `r0` to `r7` (the so-called *low* registers). +/// Other opcodes only encode a single register (which is then inferred from the opcode in question). #[derive(Clone, Copy, Debug, Eq, Ord, PartialEq, PartialOrd)] #[repr(u8)] pub enum Register { diff --git a/src/arm32/address/mod.rs b/src/arm32/shifter/mod.rs index 067cc20..e5da07b 100644 --- a/src/arm32/address/mod.rs +++ b/src/arm32/shifter/mod.rs @@ -1,4 +1,4 @@ -// Copyright 2021-2024 Gabriel Bjørnager Jensen. +// Copyright 2024 Gabriel Bjørnager Jensen. // // This file is part of Pollex. // @@ -19,50 +19,53 @@ // fero General Public License along with Pollex. // If not, see <https://www.gnu.org/licenses/>. -use crate::arm32::Register; +use crate::arm32::{Register, Unsigned}; use core::fmt::Display; -/// An addressing mode. -pub enum Address { - ArithmeticShiftRightImmediate { source: Register, shift: u32 }, +/// A shifter operand. +#[derive(Clone, Copy, Debug, Eq, PartialEq)] +pub enum Shifter { + ArithmeticShiftRightImmediate { source: Register, shift: Unsigned }, ArithmeticShiftRightRegister { source: Register, shift: Register }, - Immediage { immediate: u32 }, + Immediate { immediate: Unsigned }, - LogicalShiftLeftImmediate { source: Register, shift: u32 }, + LogicalShiftLeftImmediate { source: Register, shift: Unsigned }, LogicalShiftLeftRegister { source: Register, shift: Register }, - LogicalShiftRightImmediate { source: Register, shift: u32 }, + LogicalShiftRightImmediate { source: Register, shift: Unsigned }, LogicalShiftRightRegister { source: Register, shift: Register }, RotateRightExtend { source: Register }, + RotateRightImmediate { source: Register, shift: Unsigned }, + RotateRightRegister { source: Register, shift: Register }, } -impl Display for Address { +impl Display for Shifter { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - use Address::*; + use Shifter::*; match *self { ArithmeticShiftRightImmediate { source, shift } => { - write!(f, "{source}, ASR #{shift}") + write!(f, "{source}, ASR {shift}") }, ArithmeticShiftRightRegister { source, shift } => { write!(f, "{source}, ASR {shift}") }, - Immediage { immediate } => { + Immediate { immediate } => { write!(f, "#{immediate}<") }, LogicalShiftLeftImmediate { source, shift } => { - write!(f, "{source}, LSL #{shift}") + write!(f, "{source}, LSL {shift}") }, LogicalShiftLeftRegister { source, shift } => { @@ -70,7 +73,7 @@ impl Display for Address { }, LogicalShiftRightImmediate { source, shift } => { - write!(f, "{source}, LSR #{shift}") + write!(f, "{source}, LSR {shift}") }, LogicalShiftRightRegister { source, shift } => { @@ -81,6 +84,10 @@ impl Display for Address { write!(f, "{source}, RRX") }, + RotateRightImmediate { source, shift } => { + write!(f, "{source}, ROR {shift}") + }, + RotateRightRegister { source, shift } => { write!(f, "{source}, ROR {shift}") }, diff --git a/src/arm32/signed/mod.rs b/src/arm32/signed/mod.rs new file mode 100644 index 0000000..bd07f43 --- /dev/null +++ b/src/arm32/signed/mod.rs @@ -0,0 +1,128 @@ +// Copyright 2024 Gabriel Bjørnager Jensen. +// +// This file is part of Pollex. +// +// Pollex is free software: you can redistribute it +// and/or modify it under the terms of the GNU Af- +// fero General Public License as published by the +// Free Software Foundation, either version 3 of +// the License, or (at your option) any later ver- +// sion. +// +// Pollex is distributed in the hope that it will +// be useful, but WITHOUT ANY WARRANTY; without +// even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// Affero General Public License for more details. +// +// You should have received a copy of the GNU Af- +// fero General Public License along with Pollex. +// If not, see <https://www.gnu.org/licenses/>. + +use crate::arm32::Unsigned; + +use core::cmp::Ordering; +use core::fmt::{Display, Formatter}; +use core::ops::{Add, Div, Mul, Sub}; + +/// A signed word. +/// +/// This type defines the [`Add`], [`Sub`], [`Mul`], and [`Div`] traits for `Self` and [`i32`]. +/// Internally, these implementations use wrapping arithemtic. +#[derive(Clone, Copy, Debug, Eq, Ord, PartialEq, PartialOrd)] +#[repr(transparent)] +pub struct Signed(i32); + +impl Signed { + /// Constructs a new word. + #[inline(always)] + #[must_use] + pub const fn new(value: i32) -> Self { Self(value) } + + /// Retrieves the word's value. + #[inline(always)] + #[must_use] + pub const fn get(self) -> i32 { self.0 } + + /// Sets the value of the word. + #[inline(always)] + pub fn set(&mut self, value: i32) { self.0 = value } + + /// Reinterprets the word as unsigned. + #[inline(always)] + #[must_use] + pub const fn as_unsigned(self) -> Unsigned { Unsigned::new(self.0 as u32) } +} + +impl Add<Self> for Signed { + type Output = Self; + + #[inline(always)] + fn add(self, rhs: Self) -> Self::Output { self + rhs.get() } +} + +impl Add<i32> for Signed { + type Output = Self; + + #[inline(always)] + fn add(self, rhs: i32) -> Self::Output { Self(self.0.wrapping_add(rhs)) } +} + +impl Display for Signed { + #[inline(always)] + fn fmt(&self, f: &mut Formatter) -> core::fmt::Result { + write!(f, "#{:+}", self.0) + } +} + +impl Div<Self> for Signed { + type Output = Self; + + #[inline(always)] + fn div(self, rhs: Self) -> Self::Output { self / rhs.get() } +} + +impl Div<i32> for Signed { + type Output = Self; + + #[inline(always)] + fn div(self, rhs: i32) -> Self::Output { Self(self.0.wrapping_div(rhs)) } +} + +impl Mul<Self> for Signed { + type Output = Self; + + #[inline(always)] + fn mul(self, rhs: Self) -> Self::Output { self * rhs.get() } +} + +impl Mul<i32> for Signed { + type Output = Self; + + #[inline(always)] + fn mul(self, rhs: i32) -> Self::Output { Self(self.0.wrapping_mul(rhs)) } +} + +impl Sub<Self> for Signed { + type Output = Self; + + #[inline(always)] + fn sub(self, rhs: Self) -> Self::Output { self - rhs.get() } +} + +impl Sub<i32> for Signed { + type Output = Self; + + #[inline(always)] + fn sub(self, rhs: i32) -> Self::Output { Self(self.0.wrapping_sub(rhs)) } +} + +impl PartialEq<i32> for Signed { + #[inline(always)] + fn eq(&self, other: &i32) -> bool { self.0 == *other } +} + +impl PartialOrd<i32> for Signed { + #[inline(always)] + fn partial_cmp(&self, other: &i32) -> Option<Ordering> { self.0.partial_cmp(other) } +} diff --git a/src/arm32/thumb_opcode/mod.rs b/src/arm32/thumb_opcode/mod.rs new file mode 100644 index 0000000..8e603f8 --- /dev/null +++ b/src/arm32/thumb_opcode/mod.rs @@ -0,0 +1,58 @@ +// Copyright 2024 Gabriel Bjørnager Jensen. +// +// This file is part of Pollex. +// +// Pollex is free software: you can redistribute it +// and/or modify it under the terms of the GNU Af- +// fero General Public License as published by the +// Free Software Foundation, either version 3 of +// the License, or (at your option) any later ver- +// sion. +// +// Pollex is distributed in the hope that it will +// be useful, but WITHOUT ANY WARRANTY; without +// even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// Affero General Public License for more details. +// +// You should have received a copy of the GNU Af- +// fero General Public License along with Pollex. +// If not, see <https://www.gnu.org/licenses/>. + +use core::fmt::{Debug, Display, Formatter}; + +/// A Thumb opcode. +#[derive(Clone, Copy, Eq, PartialEq)] +#[repr(transparent)] +pub struct ThumbOpcode(u16); + +impl ThumbOpcode { + /// Creates a new opcode from a primitive. + #[inline(always)] + #[must_use] + pub const fn from_u16(value: u16) -> Self { Self(value.to_le()) } + + /// Extracts the opcode as a primitive. + #[inline(always)] + #[must_use] + pub const fn to_u16(self) -> u16 { self.0.to_le() } +} + +impl Debug for ThumbOpcode { + #[inline(always)] + fn fmt(&self, f: &mut Formatter) -> core::fmt::Result { + write!(f, "{:016b}", self.to_u16()) + } +} + +impl Display for ThumbOpcode { + #[inline(always)] + fn fmt(&self, f: &mut Formatter) -> core::fmt::Result { + write!(f, "{:#010X}", self.to_u16()) + } +} + +impl PartialEq<u16> for ThumbOpcode { + #[inline(always)] + fn eq(&self, other: &u16) -> bool { self.0 == *other } +} diff --git a/src/arm32/unsigned/mod.rs b/src/arm32/unsigned/mod.rs new file mode 100644 index 0000000..b195bf0 --- /dev/null +++ b/src/arm32/unsigned/mod.rs @@ -0,0 +1,134 @@ +// Copyright 2024 Gabriel Bjørnager Jensen. +// +// This file is part of Pollex. +// +// Pollex is free software: you can redistribute it +// and/or modify it under the terms of the GNU Af- +// fero General Public License as published by the +// Free Software Foundation, either version 3 of +// the License, or (at your option) any later ver- +// sion. +// +// Pollex is distributed in the hope that it will +// be useful, but WITHOUT ANY WARRANTY; without +// even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// Affero General Public License for more details. +// +// You should have received a copy of the GNU Af- +// fero General Public License along with Pollex. +// If not, see <https://www.gnu.org/licenses/>. + +use crate::arm32::Signed; + +use core::cmp::Ordering; +use core::fmt::{Display, Formatter}; +use core::ops::{Add, Div, Mul, Sub}; + +/// An unsigned word. +/// +/// This type defines the [`Add`], [`Sub`], [`Mul`], and [`Div`] traits for `Self` and [`u32`]. +/// Internally, these implementations use wrapping arithemtic. +#[derive(Clone, Copy, Debug, Eq, PartialEq)] +#[repr(transparent)] +pub struct Unsigned(u32); + +impl Unsigned { + /// Constructs a new word. + #[inline(always)] + #[must_use] + pub const fn new(value: u32) -> Self { Self(value) } + + /// Retrieves the word's value. + #[inline(always)] + #[must_use] + pub const fn get(self) -> u32 { self.0 } + + /// Sets the value of the word. + #[inline(always)] + pub fn set(&mut self, value: u32) { self.0 = value } + + /// Reinterprets the word as signed. + #[allow(clippy::cast_possible_wrap)] + #[inline(always)] + #[must_use] + pub const fn as_signed(self) -> Signed { Signed::new(self.0 as i32) } + + /// Adds a signed offset to the word. + #[inline(always)] + #[must_use] + pub const fn offset(self, value: i32) -> Self { Self(self.get().wrapping_add_signed(value)) } +} + +impl Add<Self> for Unsigned { + type Output = Self; + + #[inline(always)] + fn add(self, rhs: Self) -> Self::Output { self + rhs.get() } +} + +impl Add<u32> for Unsigned { + type Output = Self; + + #[inline(always)] + fn add(self, rhs: u32) -> Self::Output { Self(self.0.wrapping_add(rhs)) } +} + +impl Display for Unsigned { + #[inline(always)] + fn fmt(&self, f: &mut Formatter) -> core::fmt::Result { + write!(f, "#{}", self.0) + } +} + +impl Div<Self> for Unsigned { + type Output = Self; + + #[inline(always)] + fn div(self, rhs: Self) -> Self::Output { self / rhs.get() } +} + +impl Div<u32> for Unsigned { + type Output = Self; + + #[inline(always)] + fn div(self, rhs: u32) -> Self::Output { Self(self.0.wrapping_div(rhs)) } +} + +impl Mul<Self> for Unsigned { + type Output = Self; + + #[inline(always)] + fn mul(self, rhs: Self) -> Self::Output { self * rhs.get() } +} + +impl Mul<u32> for Unsigned { + type Output = Self; + + #[inline(always)] + fn mul(self, rhs: u32) -> Self::Output { Self(self.0.wrapping_mul(rhs)) } +} + +impl PartialEq<u32> for Unsigned { + #[inline(always)] + fn eq(&self, other: &u32) -> bool { self.0 == *other } +} + +impl PartialOrd<u32> for Unsigned { + #[inline(always)] + fn partial_cmp(&self, other: &u32) -> Option<Ordering> { self.0.partial_cmp(other) } +} + +impl Sub<Self> for Unsigned { + type Output = Self; + + #[inline(always)] + fn sub(self, rhs: Self) -> Self::Output { self - rhs.get() } +} + +impl Sub<u32> for Unsigned { + type Output = Self; + + #[inline(always)] + fn sub(self, rhs: u32) -> Self::Output { Self(self.0.wrapping_sub(rhs)) } +} diff --git a/src/error/mod.rs b/src/error/mod.rs new file mode 100644 index 0000000..99f78bb --- /dev/null +++ b/src/error/mod.rs @@ -0,0 +1,49 @@ +// Copyright 2024 Gabriel Bjørnager Jensen. +// +// This file is part of Pollex. +// +// Pollex is free software: you can redistribute it +// and/or modify it under the terms of the GNU Af- +// fero General Public License as published by the +// Free Software Foundation, either version 3 of +// the License, or (at your option) any later ver- +// sion. +// +// Pollex is distributed in the hope that it will +// be useful, but WITHOUT ANY WARRANTY; without +// even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// Affero General Public License for more details. +// +// You should have received a copy of the GNU Af- +// fero General Public License along with Pollex. +// If not, see <https://www.gnu.org/licenses/>. + +use core::fmt::{Display, Formatter}; + +/// Wrapping of [`core::result::Result`]. +pub type Result<T> = core::result::Result<T, Error>; + +/// A crate error. +#[derive(Clone, Debug)] +pub enum Error { + ImmediateTooLarge, + + InvalidImmediateValue, +} + +impl Display for Error { + fn fmt(&self, f: &mut Formatter) -> core::fmt::Result { + use Error::*; + + let message = match *self { + ImmediateTooLarge => "immediate too large", + + InvalidImmediateValue => "invalid immediate value", + }; + + f.write_str(message) + } +} + +impl core::error::Error for Error { } @@ -1,4 +1,4 @@ -// Copyright 2021-2024 Gabriel Bjørnager Jensen. +// Copyright 2024 Gabriel Bjørnager Jensen. // // This file is part of Pollex. // @@ -40,4 +40,5 @@ macro_rules! use_mod { } pub(in crate) use use_mod; -use_mod!(arch); +use_mod!(pub arch); +use_mod!(pub error); |