1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
|
/*
Copyright 2021-2023 Gabriel Jensen.
This file is part of Luma.
Luma is free software: you can redistribute it
and/or modify it under the terms of the GNU
Affero General Public License as published by
the Free Software Foundation, either version 3
of the License, or (at your option) any later
version.
Luma is distributed in the hope that it will be
useful, but WITHOUT ANY WARRANTY; without even
the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Affero General Public License for more details.
You should have received a copy of the GNU
Affero General Public License along with Luma.
If not, see <https://www.gnu.org/licenses/>.
*/
use crate::log;
use crate::cpu::{alu_exit_exception, Cpu, take_state_mut};
use crate::shifter::Shifter;
impl Cpu {
pub(super) fn isa_add(&mut self, rd: u8, rn: u8, shifter: Shifter, s: bool) {
log!("{} r{rd}, r{rn}, {shifter}", match s {
false => "add",
true => "adds",
});
take_state_mut!(state, self);
let rn_value = state.read_register(rn);
let (addend, _) = state.shifter_value(shifter);
let (result, c) = rn_value.overflowing_add(addend);
let (_, v) = (rn_value as i32).overflowing_add_unsigned(addend);
state.write_register(rd, result);
if s {
alu_exit_exception!(self, state, rd, {
let mut cpsr = state.read_cpsr() & 0b00001111111111111111111111111111;
cpsr |= (v as u32) << 0x1C;
cpsr |= (c as u32) << 0x1D;
cpsr |= ((result == 0x0) as u32) << 0x1E;
cpsr |= result & 0b10000000000000000000000000000000;
state.write_cpsr(cpsr);
});
}
}
}
|
