bjoernager/pollex
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Arm instruction manipulator.
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Gabriel Bjørnager Jensen 75a79fa55c
Update tests. Arm32: Add support for classyfying and decoding (some) Thumb opcodes; Replace immediate types with unified 'Immediate'; Replace 'from_u32_lossy' and 'from_i32_lossy' in 'Immediate' with 'new' and 'new_signed'; Replace 'as_u32', 'as_i32', 'as_u16', 'as_i16', 'as_u8', 'as_i8' in 'Immediate' with 'get' and 'get_signed'; Add 'from_bool' constructor to 'Endian' and 'Sign'; Add 'BITS' constant to 'Register', 'LowRegister', 'Immediate', 'Endian', 'Sign', 'Predicate', 'RegisterList', and 'LowRegisterList'; Add 'from_u8' constructor to 'LowRegisterList'; Add 'from_u16' constructor to 'RegisterList'.
2025-05-26 10:47:47 +02:00
src Update tests. Arm32: Add support for classyfying and decoding (some) Thumb opcodes; Replace immediate types with unified 'Immediate'; Replace 'from_u32_lossy' and 'from_i32_lossy' in 'Immediate' with 'new' and 'new_signed'; Replace 'as_u32', 'as_i32', 'as_u16', 'as_i16', 'as_u8', 'as_i8' in 'Immediate' with 'get' and 'get_signed'; Add 'from_bool' constructor to 'Endian' and 'Sign'; Add 'BITS' constant to 'Register', 'LowRegister', 'Immediate', 'Endian', 'Sign', 'Predicate', 'RegisterList', and 'LowRegisterList'; Add 'from_u8' constructor to 'LowRegisterList'; Add 'from_u16' constructor to 'RegisterList'. 2025-05-26 10:47:47 +02:00
.gitignore Fork from Luma and eAS; Add gitignore; Add changelog; Add readme; License under AGPL; Add Instruction type; Add Register type; 2024-06-11 19:17:53 +02:00
Cargo.toml Update tests. Arm32: Add support for classyfying and decoding (some) Thumb opcodes; Replace immediate types with unified 'Immediate'; Replace 'from_u32_lossy' and 'from_i32_lossy' in 'Immediate' with 'new' and 'new_signed'; Replace 'as_u32', 'as_i32', 'as_u16', 'as_i16', 'as_u8', 'as_i8' in 'Immediate' with 'get' and 'get_signed'; Add 'from_bool' constructor to 'Endian' and 'Sign'; Add 'BITS' constant to 'Register', 'LowRegister', 'Immediate', 'Endian', 'Sign', 'Predicate', 'RegisterList', and 'LowRegisterList'; Add 'from_u8' constructor to 'LowRegisterList'; Add 'from_u16' constructor to 'RegisterList'. 2025-05-26 10:47:47 +02:00
CHANGELOG.md Update tests. Arm32: Add support for classyfying and decoding (some) Thumb opcodes; Replace immediate types with unified 'Immediate'; Replace 'from_u32_lossy' and 'from_i32_lossy' in 'Immediate' with 'new' and 'new_signed'; Replace 'as_u32', 'as_i32', 'as_u16', 'as_i16', 'as_u8', 'as_i8' in 'Immediate' with 'get' and 'get_signed'; Add 'from_bool' constructor to 'Endian' and 'Sign'; Add 'BITS' constant to 'Register', 'LowRegister', 'Immediate', 'Endian', 'Sign', 'Predicate', 'RegisterList', and 'LowRegisterList'; Add 'from_u8' constructor to 'LowRegisterList'; Add 'from_u16' constructor to 'RegisterList'. 2025-05-26 10:47:47 +02:00
doc-icon.svg Relicense under MPL 2.0; Reconfigure lints; Bump Rust edition to 2024; Update copyright notices; Update code style; Update docs; Update docs icon; Update logo; Relicense logo under CC BY-SA 4.0; Set MSRV to 1.87; Restructure tests; Remove all 'Display' and 'FromStr' implementations (excluding 'Error'). Arm32: Rename 'Bflag', 'Sflag', and 'Tflag' to 'BFlag', 'SFlag', and 'TFlag', respectively; Rename 'InstructionCodec' to 'Codec'; Remove 'assert_or_err'; Temporarily remove decoding and encoding; Use short names for instructions, shifts, predicates, etc.; Add 'Immediate' type; Add 'from_u32' and 'from_i32' constructors to 'Immediate'; Add 'as_u32', 'as_i32', 'as_u16', 'as_i16', 'as_u8', and 'as_i8' conversion destructors to 'Immediate'; Implement 'Copy', 'Clone', 'PartialEq', 'Eq', 'PartialOrd', 'Ord', and 'Debug' for 'Immediate'; Implement 'PartialEq<i32>' for 'Immediate'; Unimplement 'From<{BFlag, SFlag, TFlag}>' for 'u128', 'u16', 'u32', 'u64', 'u8', and 'usize'; Remove 'UnknownMnemonic' and 'UnknownRegister' errors; Unimplement 'PartialOrd' and 'Ord' from 'Predicate'; Add 'AsrImmediate', 'AsrRegister', 'LslImmediate', 'LslRegister', 'LsrImmediate', 'LsrRegister', 'RorExtend', 'RorImmediate', and 'RorRegister' types; Add 'Register' variant to 'Shifter'; Remove 'Shifter::{from_register, as_register}'; Implement 'Copy', 'Clone', 'Debug', 'PartialEq', and 'Eq' for 'AsrImmediate', 'AsrRegister', 'LslImmediate', 'LslRegister', 'LsrImmediate', 'LsrRegister', and 'RorExtend',; Add 'decode_arm' method to 'Codec'; Implement 'From<Register', 'From<Immediate>', 'From<AsrImmediate>', 'From<AsrRegister>', 'From<LslImmediate>', 'From<LslRegister>', 'From<LsrImmediate>', 'From<LsrRegister>', and 'From<RorExtend>' for 'Shifter'; Add 'Sign' type; Implement 'Copy', 'Clone', and 'Debug' for 'Sign'; Mark 'Codec::{seek_to, skip_bytes, skip_halfwords, skip_words}' as 'const'; Reorder some 'Instruction' variant fields; Unimplement 'From<u16>' and 'PartialEq<u16>' for 'ThumbOpcode'; Unimplement 'From<ThumbOpcode>' for 'u16'; Unimplement 'From<u32>' and 'PartialEq<u32>' for 'ArmOpcode'; Unimplement 'From<ArmOpcode>' for 'u32'; Rework 'Shifter' variants. 2025-05-17 11:34:36 +02:00
LICENCE Relicense under MPL 2.0; Reconfigure lints; Bump Rust edition to 2024; Update copyright notices; Update code style; Update docs; Update docs icon; Update logo; Relicense logo under CC BY-SA 4.0; Set MSRV to 1.87; Restructure tests; Remove all 'Display' and 'FromStr' implementations (excluding 'Error'). Arm32: Rename 'Bflag', 'Sflag', and 'Tflag' to 'BFlag', 'SFlag', and 'TFlag', respectively; Rename 'InstructionCodec' to 'Codec'; Remove 'assert_or_err'; Temporarily remove decoding and encoding; Use short names for instructions, shifts, predicates, etc.; Add 'Immediate' type; Add 'from_u32' and 'from_i32' constructors to 'Immediate'; Add 'as_u32', 'as_i32', 'as_u16', 'as_i16', 'as_u8', and 'as_i8' conversion destructors to 'Immediate'; Implement 'Copy', 'Clone', 'PartialEq', 'Eq', 'PartialOrd', 'Ord', and 'Debug' for 'Immediate'; Implement 'PartialEq<i32>' for 'Immediate'; Unimplement 'From<{BFlag, SFlag, TFlag}>' for 'u128', 'u16', 'u32', 'u64', 'u8', and 'usize'; Remove 'UnknownMnemonic' and 'UnknownRegister' errors; Unimplement 'PartialOrd' and 'Ord' from 'Predicate'; Add 'AsrImmediate', 'AsrRegister', 'LslImmediate', 'LslRegister', 'LsrImmediate', 'LsrRegister', 'RorExtend', 'RorImmediate', and 'RorRegister' types; Add 'Register' variant to 'Shifter'; Remove 'Shifter::{from_register, as_register}'; Implement 'Copy', 'Clone', 'Debug', 'PartialEq', and 'Eq' for 'AsrImmediate', 'AsrRegister', 'LslImmediate', 'LslRegister', 'LsrImmediate', 'LsrRegister', and 'RorExtend',; Add 'decode_arm' method to 'Codec'; Implement 'From<Register', 'From<Immediate>', 'From<AsrImmediate>', 'From<AsrRegister>', 'From<LslImmediate>', 'From<LslRegister>', 'From<LsrImmediate>', 'From<LsrRegister>', and 'From<RorExtend>' for 'Shifter'; Add 'Sign' type; Implement 'Copy', 'Clone', and 'Debug' for 'Sign'; Mark 'Codec::{seek_to, skip_bytes, skip_halfwords, skip_words}' as 'const'; Reorder some 'Instruction' variant fields; Unimplement 'From<u16>' and 'PartialEq<u16>' for 'ThumbOpcode'; Unimplement 'From<ThumbOpcode>' for 'u16'; Unimplement 'From<u32>' and 'PartialEq<u32>' for 'ArmOpcode'; Unimplement 'From<ArmOpcode>' for 'u32'; Rework 'Shifter' variants. 2025-05-17 11:34:36 +02:00
pollex-wordmark.svg Relicense under MPL 2.0; Reconfigure lints; Bump Rust edition to 2024; Update copyright notices; Update code style; Update docs; Update docs icon; Update logo; Relicense logo under CC BY-SA 4.0; Set MSRV to 1.87; Restructure tests; Remove all 'Display' and 'FromStr' implementations (excluding 'Error'). Arm32: Rename 'Bflag', 'Sflag', and 'Tflag' to 'BFlag', 'SFlag', and 'TFlag', respectively; Rename 'InstructionCodec' to 'Codec'; Remove 'assert_or_err'; Temporarily remove decoding and encoding; Use short names for instructions, shifts, predicates, etc.; Add 'Immediate' type; Add 'from_u32' and 'from_i32' constructors to 'Immediate'; Add 'as_u32', 'as_i32', 'as_u16', 'as_i16', 'as_u8', and 'as_i8' conversion destructors to 'Immediate'; Implement 'Copy', 'Clone', 'PartialEq', 'Eq', 'PartialOrd', 'Ord', and 'Debug' for 'Immediate'; Implement 'PartialEq<i32>' for 'Immediate'; Unimplement 'From<{BFlag, SFlag, TFlag}>' for 'u128', 'u16', 'u32', 'u64', 'u8', and 'usize'; Remove 'UnknownMnemonic' and 'UnknownRegister' errors; Unimplement 'PartialOrd' and 'Ord' from 'Predicate'; Add 'AsrImmediate', 'AsrRegister', 'LslImmediate', 'LslRegister', 'LsrImmediate', 'LsrRegister', 'RorExtend', 'RorImmediate', and 'RorRegister' types; Add 'Register' variant to 'Shifter'; Remove 'Shifter::{from_register, as_register}'; Implement 'Copy', 'Clone', 'Debug', 'PartialEq', and 'Eq' for 'AsrImmediate', 'AsrRegister', 'LslImmediate', 'LslRegister', 'LsrImmediate', 'LsrRegister', and 'RorExtend',; Add 'decode_arm' method to 'Codec'; Implement 'From<Register', 'From<Immediate>', 'From<AsrImmediate>', 'From<AsrRegister>', 'From<LslImmediate>', 'From<LslRegister>', 'From<LsrImmediate>', 'From<LsrRegister>', and 'From<RorExtend>' for 'Shifter'; Add 'Sign' type; Implement 'Copy', 'Clone', and 'Debug' for 'Sign'; Mark 'Codec::{seek_to, skip_bytes, skip_halfwords, skip_words}' as 'const'; Reorder some 'Instruction' variant fields; Unimplement 'From<u16>' and 'PartialEq<u16>' for 'ThumbOpcode'; Unimplement 'From<ThumbOpcode>' for 'u16'; Unimplement 'From<u32>' and 'PartialEq<u32>' for 'ArmOpcode'; Unimplement 'From<ArmOpcode>' for 'u32'; Rework 'Shifter' variants. 2025-05-17 11:34:36 +02:00
pollex.svg Relicense under MPL 2.0; Reconfigure lints; Bump Rust edition to 2024; Update copyright notices; Update code style; Update docs; Update docs icon; Update logo; Relicense logo under CC BY-SA 4.0; Set MSRV to 1.87; Restructure tests; Remove all 'Display' and 'FromStr' implementations (excluding 'Error'). Arm32: Rename 'Bflag', 'Sflag', and 'Tflag' to 'BFlag', 'SFlag', and 'TFlag', respectively; Rename 'InstructionCodec' to 'Codec'; Remove 'assert_or_err'; Temporarily remove decoding and encoding; Use short names for instructions, shifts, predicates, etc.; Add 'Immediate' type; Add 'from_u32' and 'from_i32' constructors to 'Immediate'; Add 'as_u32', 'as_i32', 'as_u16', 'as_i16', 'as_u8', and 'as_i8' conversion destructors to 'Immediate'; Implement 'Copy', 'Clone', 'PartialEq', 'Eq', 'PartialOrd', 'Ord', and 'Debug' for 'Immediate'; Implement 'PartialEq<i32>' for 'Immediate'; Unimplement 'From<{BFlag, SFlag, TFlag}>' for 'u128', 'u16', 'u32', 'u64', 'u8', and 'usize'; Remove 'UnknownMnemonic' and 'UnknownRegister' errors; Unimplement 'PartialOrd' and 'Ord' from 'Predicate'; Add 'AsrImmediate', 'AsrRegister', 'LslImmediate', 'LslRegister', 'LsrImmediate', 'LsrRegister', 'RorExtend', 'RorImmediate', and 'RorRegister' types; Add 'Register' variant to 'Shifter'; Remove 'Shifter::{from_register, as_register}'; Implement 'Copy', 'Clone', 'Debug', 'PartialEq', and 'Eq' for 'AsrImmediate', 'AsrRegister', 'LslImmediate', 'LslRegister', 'LsrImmediate', 'LsrRegister', and 'RorExtend',; Add 'decode_arm' method to 'Codec'; Implement 'From<Register', 'From<Immediate>', 'From<AsrImmediate>', 'From<AsrRegister>', 'From<LslImmediate>', 'From<LslRegister>', 'From<LsrImmediate>', 'From<LsrRegister>', and 'From<RorExtend>' for 'Shifter'; Add 'Sign' type; Implement 'Copy', 'Clone', and 'Debug' for 'Sign'; Mark 'Codec::{seek_to, skip_bytes, skip_halfwords, skip_words}' as 'const'; Reorder some 'Instruction' variant fields; Unimplement 'From<u16>' and 'PartialEq<u16>' for 'ThumbOpcode'; Unimplement 'From<ThumbOpcode>' for 'u16'; Unimplement 'From<u32>' and 'PartialEq<u32>' for 'ArmOpcode'; Unimplement 'From<ArmOpcode>' for 'u32'; Rework 'Shifter' variants. 2025-05-17 11:34:36 +02:00
README.md Update docs; Update readme; Remove crate-level 'Error' and 'Result' types; Implement 'From<Infallible>' for error types. Arm32: Add 'arm' and 'thumb' modules; Correctly name 'RorExtend' as 'Rrx'; Remove 'Instruction'; Add 'arm::Instruction' and 'thumb::Instruction' types; Add 'LowRegister' type; Implement 'Clone', 'Copy', 'Debug', 'Eq', 'PartialEq', 'Ord', and 'PartialOrd' for 'LowRegister'; Implement 'From<LowRegister>' for 'Register'; Add 'as_low' method to 'Register'; Add 'from_u8' constructor to 'LowRegister'; Add 'into_register' destructor to 'LowRegister'; Remove flag types; Add 'arm::Tag' and 'thumb::Tag' types; Implement 'Clone', 'Copy', 'Debug', 'Eq', and 'PartialEq' for 'arm::Tag' and 'thumb::Tag'; Rework 'arm::Opcode' and 'thumb::Opcode'; Remove 'arm::Opcode::{from_u32, to_u32}'; Remove 'thumb::Opcode::{from_u16, to_u16}'; Add 'classify' constructor to 'arm::Opcode' and 'thumb::Opcode'; Remove 'Codec'; Replace 'Immediate' with 'Immediate3', 'Immediate5', 'Immediate7', 'Immediate8', 'Immediate11', 'Immediate12', 'Immediate16', and 'Immediate24'; Replace 'from_u32' and 'from_i32' immediate constructors with 'from_u32_lossy' and 'from_i32_lossy'; Remove 'Register' variant from 'Shifter'; Add 'from_register' constructor to 'Shifter'; Add 'as_register' method to 'Shifter'; Add 'decode' method to 'arm::Opcode' and 'thumb::Opcode'; Add 'encode' method to 'arm::Instruction' and 'thumb::Instruction'; Add 'error' module; Add 'ThumbClassifyError' and 'ArmClassifyError' errors; Add 'tag' method to 'arm::Instruction' and 'thumb::Instruction'; Implement 'Clone', 'Debug', 'Eq', and 'PartialEq' for 'arm::Instruction' and 'thumb::Instruction'; Add 'raw', 'tag', and 'address' methods to 'arm::Opcode' and 'thumb::Opcode'; Rename 'SIZE' to 'RAW_SIZE' in 'arm::Opcode' and 'thumb::Opcode'. 2025-05-22 11:49:25 +02:00

README.md

Pollex

Pollex is a Rust-written library for manipulating instructions of Arm ISAs.

Acknowledgements

Copyright & Licensing

Copyright 2024-2025 Gabriel Bjørnager Jensen.

The Source Code Forms of this project are – where noted as such – subject to the terms of the Mozilla Public License, version 2.0. If a copy of the MPL was not distributed with this project, you can obtain one at https://mozilla.org/MPL/2.0/.

Trademarks

Arm and Thumb are registered trademarks of Arm Limited in the E.U.