896 lines
32 KiB
Rust
896 lines
32 KiB
Rust
use crate::abi::Size;
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use crate::spec::Target;
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use rustc_data_structures::fx::{FxHashMap, FxHashSet};
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use rustc_macros::HashStable_Generic;
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use rustc_span::Symbol;
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use std::fmt;
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use std::str::FromStr;
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macro_rules! def_reg_class {
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($arch:ident $arch_regclass:ident {
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$(
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$class:ident,
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)*
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}) => {
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#[derive(Copy, Clone, Encodable, Decodable, Debug, Eq, PartialEq, PartialOrd, Hash, HashStable_Generic)]
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#[allow(non_camel_case_types)]
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pub enum $arch_regclass {
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$($class,)*
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}
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impl $arch_regclass {
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pub fn name(self) -> rustc_span::Symbol {
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match self {
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$(Self::$class => rustc_span::symbol::sym::$class,)*
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}
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}
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pub fn parse(_arch: super::InlineAsmArch, name: rustc_span::Symbol) -> Result<Self, &'static str> {
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match name {
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$(
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rustc_span::sym::$class => Ok(Self::$class),
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)*
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_ => Err("unknown register class"),
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}
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}
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}
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pub(super) fn regclass_map() -> rustc_data_structures::fx::FxHashMap<
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super::InlineAsmRegClass,
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rustc_data_structures::fx::FxHashSet<super::InlineAsmReg>,
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> {
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use rustc_data_structures::fx::{FxHashMap, FxHashSet};
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use super::InlineAsmRegClass;
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let mut map = FxHashMap::default();
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$(
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map.insert(InlineAsmRegClass::$arch($arch_regclass::$class), FxHashSet::default());
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)*
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map
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}
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}
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}
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macro_rules! def_regs {
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($arch:ident $arch_reg:ident $arch_regclass:ident {
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$(
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$reg:ident: $class:ident $(, $extra_class:ident)* = [$reg_name:literal $(, $alias:literal)*] $(% $filter:ident)?,
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)*
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$(
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#error = [$($bad_reg:literal),+] => $error:literal,
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)*
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}) => {
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#[allow(unreachable_code)]
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#[derive(Copy, Clone, Encodable, Decodable, Debug, Eq, PartialEq, PartialOrd, Hash, HashStable_Generic)]
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#[allow(non_camel_case_types)]
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pub enum $arch_reg {
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$($reg,)*
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}
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impl $arch_reg {
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pub fn name(self) -> &'static str {
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match self {
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$(Self::$reg => $reg_name,)*
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}
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}
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pub fn reg_class(self) -> $arch_regclass {
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match self {
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$(Self::$reg => $arch_regclass::$class,)*
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}
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}
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pub fn parse(
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_arch: super::InlineAsmArch,
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mut _has_feature: impl FnMut(&str) -> bool,
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_target: &crate::spec::Target,
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name: &str,
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) -> Result<Self, &'static str> {
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match name {
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$(
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$($alias)|* | $reg_name => {
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$($filter(_arch, &mut _has_feature, _target)?;)?
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Ok(Self::$reg)
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}
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)*
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$(
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$($bad_reg)|* => Err($error),
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)*
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_ => Err("unknown register"),
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}
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}
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}
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pub(super) fn fill_reg_map(
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_arch: super::InlineAsmArch,
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mut _has_feature: impl FnMut(&str) -> bool,
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_target: &crate::spec::Target,
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_map: &mut rustc_data_structures::fx::FxHashMap<
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super::InlineAsmRegClass,
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rustc_data_structures::fx::FxHashSet<super::InlineAsmReg>,
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>,
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) {
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#[allow(unused_imports)]
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use super::{InlineAsmReg, InlineAsmRegClass};
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$(
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if $($filter(_arch, &mut _has_feature, _target).is_ok() &&)? true {
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if let Some(set) = _map.get_mut(&InlineAsmRegClass::$arch($arch_regclass::$class)) {
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set.insert(InlineAsmReg::$arch($arch_reg::$reg));
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}
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$(
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if let Some(set) = _map.get_mut(&InlineAsmRegClass::$arch($arch_regclass::$extra_class)) {
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set.insert(InlineAsmReg::$arch($arch_reg::$reg));
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}
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)*
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}
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)*
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}
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}
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}
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macro_rules! types {
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(
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$(_ : $($ty:expr),+;)?
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$($feature:literal: $($ty2:expr),+;)*
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) => {
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{
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use super::InlineAsmType::*;
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&[
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$($(
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($ty, None),
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)*)?
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$($(
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($ty2, Some($feature)),
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)*)*
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]
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}
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};
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}
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mod aarch64;
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mod arm;
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mod bpf;
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mod hexagon;
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mod mips;
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mod nvptx;
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mod powerpc;
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mod riscv;
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mod spirv;
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mod wasm;
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mod x86;
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pub use aarch64::{AArch64InlineAsmReg, AArch64InlineAsmRegClass};
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pub use arm::{ArmInlineAsmReg, ArmInlineAsmRegClass};
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pub use bpf::{BpfInlineAsmReg, BpfInlineAsmRegClass};
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pub use hexagon::{HexagonInlineAsmReg, HexagonInlineAsmRegClass};
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pub use mips::{MipsInlineAsmReg, MipsInlineAsmRegClass};
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pub use nvptx::{NvptxInlineAsmReg, NvptxInlineAsmRegClass};
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pub use powerpc::{PowerPCInlineAsmReg, PowerPCInlineAsmRegClass};
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pub use riscv::{RiscVInlineAsmReg, RiscVInlineAsmRegClass};
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pub use spirv::{SpirVInlineAsmReg, SpirVInlineAsmRegClass};
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pub use wasm::{WasmInlineAsmReg, WasmInlineAsmRegClass};
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pub use x86::{X86InlineAsmReg, X86InlineAsmRegClass};
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#[derive(Copy, Clone, Encodable, Decodable, Debug, Eq, PartialEq, Hash)]
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pub enum InlineAsmArch {
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X86,
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X86_64,
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Arm,
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AArch64,
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RiscV32,
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RiscV64,
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Nvptx64,
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Hexagon,
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Mips,
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Mips64,
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PowerPC,
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PowerPC64,
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SpirV,
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Wasm32,
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Bpf,
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}
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impl FromStr for InlineAsmArch {
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type Err = ();
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fn from_str(s: &str) -> Result<InlineAsmArch, ()> {
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match s {
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"x86" => Ok(Self::X86),
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"x86_64" => Ok(Self::X86_64),
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"arm" => Ok(Self::Arm),
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"aarch64" => Ok(Self::AArch64),
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"riscv32" => Ok(Self::RiscV32),
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"riscv64" => Ok(Self::RiscV64),
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"nvptx64" => Ok(Self::Nvptx64),
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"powerpc" => Ok(Self::PowerPC),
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"powerpc64" => Ok(Self::PowerPC64),
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"hexagon" => Ok(Self::Hexagon),
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"mips" => Ok(Self::Mips),
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"mips64" => Ok(Self::Mips64),
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"spirv" => Ok(Self::SpirV),
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"wasm32" => Ok(Self::Wasm32),
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"bpf" => Ok(Self::Bpf),
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_ => Err(()),
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}
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}
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}
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#[derive(
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Copy,
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Clone,
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Encodable,
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Decodable,
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Debug,
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Eq,
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PartialEq,
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PartialOrd,
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Hash,
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HashStable_Generic
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)]
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pub enum InlineAsmReg {
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X86(X86InlineAsmReg),
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Arm(ArmInlineAsmReg),
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AArch64(AArch64InlineAsmReg),
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RiscV(RiscVInlineAsmReg),
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Nvptx(NvptxInlineAsmReg),
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PowerPC(PowerPCInlineAsmReg),
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Hexagon(HexagonInlineAsmReg),
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Mips(MipsInlineAsmReg),
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SpirV(SpirVInlineAsmReg),
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Wasm(WasmInlineAsmReg),
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Bpf(BpfInlineAsmReg),
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// Placeholder for invalid register constraints for the current target
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Err,
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}
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impl InlineAsmReg {
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pub fn name(self) -> &'static str {
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match self {
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Self::X86(r) => r.name(),
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Self::Arm(r) => r.name(),
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Self::AArch64(r) => r.name(),
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Self::RiscV(r) => r.name(),
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Self::PowerPC(r) => r.name(),
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Self::Hexagon(r) => r.name(),
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Self::Mips(r) => r.name(),
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Self::Bpf(r) => r.name(),
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Self::Err => "<reg>",
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}
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}
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pub fn reg_class(self) -> InlineAsmRegClass {
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match self {
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Self::X86(r) => InlineAsmRegClass::X86(r.reg_class()),
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Self::Arm(r) => InlineAsmRegClass::Arm(r.reg_class()),
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Self::AArch64(r) => InlineAsmRegClass::AArch64(r.reg_class()),
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Self::RiscV(r) => InlineAsmRegClass::RiscV(r.reg_class()),
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Self::PowerPC(r) => InlineAsmRegClass::PowerPC(r.reg_class()),
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Self::Hexagon(r) => InlineAsmRegClass::Hexagon(r.reg_class()),
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Self::Mips(r) => InlineAsmRegClass::Mips(r.reg_class()),
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Self::Bpf(r) => InlineAsmRegClass::Bpf(r.reg_class()),
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Self::Err => InlineAsmRegClass::Err,
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}
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}
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pub fn parse(
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arch: InlineAsmArch,
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has_feature: impl FnMut(&str) -> bool,
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target: &Target,
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name: Symbol,
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) -> Result<Self, &'static str> {
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// FIXME: use direct symbol comparison for register names
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// Use `Symbol::as_str` instead of `Symbol::with` here because `has_feature` may access `Symbol`.
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let name = name.as_str();
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Ok(match arch {
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InlineAsmArch::X86 | InlineAsmArch::X86_64 => {
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Self::X86(X86InlineAsmReg::parse(arch, has_feature, target, &name)?)
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}
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InlineAsmArch::Arm => {
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Self::Arm(ArmInlineAsmReg::parse(arch, has_feature, target, &name)?)
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}
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InlineAsmArch::AArch64 => {
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Self::AArch64(AArch64InlineAsmReg::parse(arch, has_feature, target, &name)?)
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}
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InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {
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Self::RiscV(RiscVInlineAsmReg::parse(arch, has_feature, target, &name)?)
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}
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InlineAsmArch::Nvptx64 => {
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Self::Nvptx(NvptxInlineAsmReg::parse(arch, has_feature, target, &name)?)
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}
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InlineAsmArch::PowerPC | InlineAsmArch::PowerPC64 => {
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Self::PowerPC(PowerPCInlineAsmReg::parse(arch, has_feature, target, &name)?)
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}
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InlineAsmArch::Hexagon => {
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Self::Hexagon(HexagonInlineAsmReg::parse(arch, has_feature, target, &name)?)
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}
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InlineAsmArch::Mips | InlineAsmArch::Mips64 => {
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Self::Mips(MipsInlineAsmReg::parse(arch, has_feature, target, &name)?)
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}
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InlineAsmArch::SpirV => {
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Self::SpirV(SpirVInlineAsmReg::parse(arch, has_feature, target, &name)?)
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}
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InlineAsmArch::Wasm32 => {
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Self::Wasm(WasmInlineAsmReg::parse(arch, has_feature, target, &name)?)
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}
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InlineAsmArch::Bpf => {
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Self::Bpf(BpfInlineAsmReg::parse(arch, has_feature, target, &name)?)
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}
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})
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}
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// NOTE: This function isn't used at the moment, but is needed to support
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// falling back to an external assembler.
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pub fn emit(
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self,
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out: &mut dyn fmt::Write,
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arch: InlineAsmArch,
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modifier: Option<char>,
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) -> fmt::Result {
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match self {
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Self::X86(r) => r.emit(out, arch, modifier),
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Self::Arm(r) => r.emit(out, arch, modifier),
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Self::AArch64(r) => r.emit(out, arch, modifier),
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Self::RiscV(r) => r.emit(out, arch, modifier),
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Self::PowerPC(r) => r.emit(out, arch, modifier),
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Self::Hexagon(r) => r.emit(out, arch, modifier),
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Self::Mips(r) => r.emit(out, arch, modifier),
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Self::Bpf(r) => r.emit(out, arch, modifier),
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Self::Err => unreachable!("Use of InlineAsmReg::Err"),
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}
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}
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pub fn overlapping_regs(self, mut cb: impl FnMut(InlineAsmReg)) {
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match self {
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Self::X86(r) => r.overlapping_regs(|r| cb(Self::X86(r))),
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Self::Arm(r) => r.overlapping_regs(|r| cb(Self::Arm(r))),
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Self::AArch64(_) => cb(self),
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Self::RiscV(_) => cb(self),
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Self::PowerPC(_) => cb(self),
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Self::Hexagon(r) => r.overlapping_regs(|r| cb(Self::Hexagon(r))),
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Self::Mips(_) => cb(self),
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Self::Bpf(r) => r.overlapping_regs(|r| cb(Self::Bpf(r))),
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Self::Err => unreachable!("Use of InlineAsmReg::Err"),
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}
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}
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}
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#[derive(
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Copy,
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Clone,
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Encodable,
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Decodable,
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Debug,
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Eq,
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PartialEq,
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PartialOrd,
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Hash,
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HashStable_Generic
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)]
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pub enum InlineAsmRegClass {
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X86(X86InlineAsmRegClass),
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Arm(ArmInlineAsmRegClass),
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AArch64(AArch64InlineAsmRegClass),
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RiscV(RiscVInlineAsmRegClass),
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Nvptx(NvptxInlineAsmRegClass),
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PowerPC(PowerPCInlineAsmRegClass),
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Hexagon(HexagonInlineAsmRegClass),
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Mips(MipsInlineAsmRegClass),
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SpirV(SpirVInlineAsmRegClass),
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Wasm(WasmInlineAsmRegClass),
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Bpf(BpfInlineAsmRegClass),
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// Placeholder for invalid register constraints for the current target
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Err,
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}
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impl InlineAsmRegClass {
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pub fn name(self) -> Symbol {
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match self {
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Self::X86(r) => r.name(),
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Self::Arm(r) => r.name(),
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Self::AArch64(r) => r.name(),
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Self::RiscV(r) => r.name(),
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Self::Nvptx(r) => r.name(),
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Self::PowerPC(r) => r.name(),
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Self::Hexagon(r) => r.name(),
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Self::Mips(r) => r.name(),
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Self::SpirV(r) => r.name(),
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Self::Wasm(r) => r.name(),
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Self::Bpf(r) => r.name(),
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Self::Err => rustc_span::symbol::sym::reg,
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}
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}
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/// Returns a suggested register class to use for this type. This is called
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/// after type checking via `supported_types` fails to give a better error
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/// message to the user.
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pub fn suggest_class(self, arch: InlineAsmArch, ty: InlineAsmType) -> Option<Self> {
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match self {
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Self::X86(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::X86),
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Self::Arm(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Arm),
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Self::AArch64(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::AArch64),
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Self::RiscV(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::RiscV),
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Self::Nvptx(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Nvptx),
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Self::PowerPC(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::PowerPC),
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Self::Hexagon(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Hexagon),
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Self::Mips(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Mips),
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Self::SpirV(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::SpirV),
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Self::Wasm(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Wasm),
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Self::Bpf(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Bpf),
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Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),
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}
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}
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/// Returns a suggested template modifier to use for this type and an
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/// example of a register named formatted with it.
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///
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/// Such suggestions are useful if a type smaller than the full register
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/// size is used and a modifier can be used to point to the subregister of
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/// the correct size.
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pub fn suggest_modifier(
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self,
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arch: InlineAsmArch,
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ty: InlineAsmType,
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) -> Option<(char, &'static str)> {
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match self {
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Self::X86(r) => r.suggest_modifier(arch, ty),
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Self::Arm(r) => r.suggest_modifier(arch, ty),
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Self::AArch64(r) => r.suggest_modifier(arch, ty),
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Self::RiscV(r) => r.suggest_modifier(arch, ty),
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Self::Nvptx(r) => r.suggest_modifier(arch, ty),
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Self::PowerPC(r) => r.suggest_modifier(arch, ty),
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Self::Hexagon(r) => r.suggest_modifier(arch, ty),
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Self::Mips(r) => r.suggest_modifier(arch, ty),
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Self::SpirV(r) => r.suggest_modifier(arch, ty),
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Self::Wasm(r) => r.suggest_modifier(arch, ty),
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Self::Bpf(r) => r.suggest_modifier(arch, ty),
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Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),
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}
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}
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|
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/// Returns the default modifier for this register and an example of a
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/// register named formatted with it.
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///
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/// This is only needed when the register class can suggest a modifier, so
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/// that the user can be shown how to get the default behavior without a
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/// warning.
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pub fn default_modifier(self, arch: InlineAsmArch) -> Option<(char, &'static str)> {
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|
match self {
|
|
Self::X86(r) => r.default_modifier(arch),
|
|
Self::Arm(r) => r.default_modifier(arch),
|
|
Self::AArch64(r) => r.default_modifier(arch),
|
|
Self::RiscV(r) => r.default_modifier(arch),
|
|
Self::Nvptx(r) => r.default_modifier(arch),
|
|
Self::PowerPC(r) => r.default_modifier(arch),
|
|
Self::Hexagon(r) => r.default_modifier(arch),
|
|
Self::Mips(r) => r.default_modifier(arch),
|
|
Self::SpirV(r) => r.default_modifier(arch),
|
|
Self::Wasm(r) => r.default_modifier(arch),
|
|
Self::Bpf(r) => r.default_modifier(arch),
|
|
Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),
|
|
}
|
|
}
|
|
|
|
/// Returns a list of supported types for this register class, each with an
|
|
/// options target feature required to use this type.
|
|
pub fn supported_types(
|
|
self,
|
|
arch: InlineAsmArch,
|
|
) -> &'static [(InlineAsmType, Option<&'static str>)] {
|
|
match self {
|
|
Self::X86(r) => r.supported_types(arch),
|
|
Self::Arm(r) => r.supported_types(arch),
|
|
Self::AArch64(r) => r.supported_types(arch),
|
|
Self::RiscV(r) => r.supported_types(arch),
|
|
Self::Nvptx(r) => r.supported_types(arch),
|
|
Self::PowerPC(r) => r.supported_types(arch),
|
|
Self::Hexagon(r) => r.supported_types(arch),
|
|
Self::Mips(r) => r.supported_types(arch),
|
|
Self::SpirV(r) => r.supported_types(arch),
|
|
Self::Wasm(r) => r.supported_types(arch),
|
|
Self::Bpf(r) => r.supported_types(arch),
|
|
Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),
|
|
}
|
|
}
|
|
|
|
pub fn parse(arch: InlineAsmArch, name: Symbol) -> Result<Self, &'static str> {
|
|
Ok(match arch {
|
|
InlineAsmArch::X86 | InlineAsmArch::X86_64 => {
|
|
Self::X86(X86InlineAsmRegClass::parse(arch, name)?)
|
|
}
|
|
InlineAsmArch::Arm => Self::Arm(ArmInlineAsmRegClass::parse(arch, name)?),
|
|
InlineAsmArch::AArch64 => Self::AArch64(AArch64InlineAsmRegClass::parse(arch, name)?),
|
|
InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {
|
|
Self::RiscV(RiscVInlineAsmRegClass::parse(arch, name)?)
|
|
}
|
|
InlineAsmArch::Nvptx64 => Self::Nvptx(NvptxInlineAsmRegClass::parse(arch, name)?),
|
|
InlineAsmArch::PowerPC | InlineAsmArch::PowerPC64 => {
|
|
Self::PowerPC(PowerPCInlineAsmRegClass::parse(arch, name)?)
|
|
}
|
|
InlineAsmArch::Hexagon => Self::Hexagon(HexagonInlineAsmRegClass::parse(arch, name)?),
|
|
InlineAsmArch::Mips | InlineAsmArch::Mips64 => {
|
|
Self::Mips(MipsInlineAsmRegClass::parse(arch, name)?)
|
|
}
|
|
InlineAsmArch::SpirV => Self::SpirV(SpirVInlineAsmRegClass::parse(arch, name)?),
|
|
InlineAsmArch::Wasm32 => Self::Wasm(WasmInlineAsmRegClass::parse(arch, name)?),
|
|
InlineAsmArch::Bpf => Self::Bpf(BpfInlineAsmRegClass::parse(arch, name)?),
|
|
})
|
|
}
|
|
|
|
/// Returns the list of template modifiers that can be used with this
|
|
/// register class.
|
|
pub fn valid_modifiers(self, arch: InlineAsmArch) -> &'static [char] {
|
|
match self {
|
|
Self::X86(r) => r.valid_modifiers(arch),
|
|
Self::Arm(r) => r.valid_modifiers(arch),
|
|
Self::AArch64(r) => r.valid_modifiers(arch),
|
|
Self::RiscV(r) => r.valid_modifiers(arch),
|
|
Self::Nvptx(r) => r.valid_modifiers(arch),
|
|
Self::PowerPC(r) => r.valid_modifiers(arch),
|
|
Self::Hexagon(r) => r.valid_modifiers(arch),
|
|
Self::Mips(r) => r.valid_modifiers(arch),
|
|
Self::SpirV(r) => r.valid_modifiers(arch),
|
|
Self::Wasm(r) => r.valid_modifiers(arch),
|
|
Self::Bpf(r) => r.valid_modifiers(arch),
|
|
Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),
|
|
}
|
|
}
|
|
|
|
/// Returns whether registers in this class can only be used as clobbers
|
|
/// and not as inputs/outputs.
|
|
pub fn is_clobber_only(self, arch: InlineAsmArch) -> bool {
|
|
self.supported_types(arch).is_empty()
|
|
}
|
|
}
|
|
|
|
#[derive(
|
|
Copy,
|
|
Clone,
|
|
Encodable,
|
|
Decodable,
|
|
Debug,
|
|
Eq,
|
|
PartialEq,
|
|
PartialOrd,
|
|
Hash,
|
|
HashStable_Generic
|
|
)]
|
|
pub enum InlineAsmRegOrRegClass {
|
|
Reg(InlineAsmReg),
|
|
RegClass(InlineAsmRegClass),
|
|
}
|
|
|
|
impl InlineAsmRegOrRegClass {
|
|
pub fn reg_class(self) -> InlineAsmRegClass {
|
|
match self {
|
|
Self::Reg(r) => r.reg_class(),
|
|
Self::RegClass(r) => r,
|
|
}
|
|
}
|
|
}
|
|
|
|
impl fmt::Display for InlineAsmRegOrRegClass {
|
|
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
|
|
match self {
|
|
Self::Reg(r) => write!(f, "\"{}\"", r.name()),
|
|
Self::RegClass(r) => write!(f, "{}", r.name()),
|
|
}
|
|
}
|
|
}
|
|
|
|
/// Set of types which can be used with a particular register class.
|
|
#[derive(Copy, Clone, Debug, Eq, PartialEq)]
|
|
pub enum InlineAsmType {
|
|
I8,
|
|
I16,
|
|
I32,
|
|
I64,
|
|
I128,
|
|
F32,
|
|
F64,
|
|
VecI8(u64),
|
|
VecI16(u64),
|
|
VecI32(u64),
|
|
VecI64(u64),
|
|
VecI128(u64),
|
|
VecF32(u64),
|
|
VecF64(u64),
|
|
}
|
|
|
|
impl InlineAsmType {
|
|
pub fn is_integer(self) -> bool {
|
|
matches!(self, Self::I8 | Self::I16 | Self::I32 | Self::I64 | Self::I128)
|
|
}
|
|
|
|
pub fn size(self) -> Size {
|
|
Size::from_bytes(match self {
|
|
Self::I8 => 1,
|
|
Self::I16 => 2,
|
|
Self::I32 => 4,
|
|
Self::I64 => 8,
|
|
Self::I128 => 16,
|
|
Self::F32 => 4,
|
|
Self::F64 => 8,
|
|
Self::VecI8(n) => n * 1,
|
|
Self::VecI16(n) => n * 2,
|
|
Self::VecI32(n) => n * 4,
|
|
Self::VecI64(n) => n * 8,
|
|
Self::VecI128(n) => n * 16,
|
|
Self::VecF32(n) => n * 4,
|
|
Self::VecF64(n) => n * 8,
|
|
})
|
|
}
|
|
}
|
|
|
|
impl fmt::Display for InlineAsmType {
|
|
fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
|
|
match *self {
|
|
Self::I8 => f.write_str("i8"),
|
|
Self::I16 => f.write_str("i16"),
|
|
Self::I32 => f.write_str("i32"),
|
|
Self::I64 => f.write_str("i64"),
|
|
Self::I128 => f.write_str("i128"),
|
|
Self::F32 => f.write_str("f32"),
|
|
Self::F64 => f.write_str("f64"),
|
|
Self::VecI8(n) => write!(f, "i8x{}", n),
|
|
Self::VecI16(n) => write!(f, "i16x{}", n),
|
|
Self::VecI32(n) => write!(f, "i32x{}", n),
|
|
Self::VecI64(n) => write!(f, "i64x{}", n),
|
|
Self::VecI128(n) => write!(f, "i128x{}", n),
|
|
Self::VecF32(n) => write!(f, "f32x{}", n),
|
|
Self::VecF64(n) => write!(f, "f64x{}", n),
|
|
}
|
|
}
|
|
}
|
|
|
|
/// Returns the full set of allocatable registers for a given architecture.
|
|
///
|
|
/// The registers are structured as a map containing the set of allocatable
|
|
/// registers in each register class. A particular register may be allocatable
|
|
/// from multiple register classes, in which case it will appear multiple times
|
|
/// in the map.
|
|
// NOTE: This function isn't used at the moment, but is needed to support
|
|
// falling back to an external assembler.
|
|
pub fn allocatable_registers(
|
|
arch: InlineAsmArch,
|
|
has_feature: impl FnMut(&str) -> bool,
|
|
target: &crate::spec::Target,
|
|
) -> FxHashMap<InlineAsmRegClass, FxHashSet<InlineAsmReg>> {
|
|
match arch {
|
|
InlineAsmArch::X86 | InlineAsmArch::X86_64 => {
|
|
let mut map = x86::regclass_map();
|
|
x86::fill_reg_map(arch, has_feature, target, &mut map);
|
|
map
|
|
}
|
|
InlineAsmArch::Arm => {
|
|
let mut map = arm::regclass_map();
|
|
arm::fill_reg_map(arch, has_feature, target, &mut map);
|
|
map
|
|
}
|
|
InlineAsmArch::AArch64 => {
|
|
let mut map = aarch64::regclass_map();
|
|
aarch64::fill_reg_map(arch, has_feature, target, &mut map);
|
|
map
|
|
}
|
|
InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {
|
|
let mut map = riscv::regclass_map();
|
|
riscv::fill_reg_map(arch, has_feature, target, &mut map);
|
|
map
|
|
}
|
|
InlineAsmArch::Nvptx64 => {
|
|
let mut map = nvptx::regclass_map();
|
|
nvptx::fill_reg_map(arch, has_feature, target, &mut map);
|
|
map
|
|
}
|
|
InlineAsmArch::PowerPC | InlineAsmArch::PowerPC64 => {
|
|
let mut map = powerpc::regclass_map();
|
|
powerpc::fill_reg_map(arch, has_feature, target, &mut map);
|
|
map
|
|
}
|
|
InlineAsmArch::Hexagon => {
|
|
let mut map = hexagon::regclass_map();
|
|
hexagon::fill_reg_map(arch, has_feature, target, &mut map);
|
|
map
|
|
}
|
|
InlineAsmArch::Mips | InlineAsmArch::Mips64 => {
|
|
let mut map = mips::regclass_map();
|
|
mips::fill_reg_map(arch, has_feature, target, &mut map);
|
|
map
|
|
}
|
|
InlineAsmArch::SpirV => {
|
|
let mut map = spirv::regclass_map();
|
|
spirv::fill_reg_map(arch, has_feature, target, &mut map);
|
|
map
|
|
}
|
|
InlineAsmArch::Wasm32 => {
|
|
let mut map = wasm::regclass_map();
|
|
wasm::fill_reg_map(arch, has_feature, target, &mut map);
|
|
map
|
|
}
|
|
InlineAsmArch::Bpf => {
|
|
let mut map = bpf::regclass_map();
|
|
bpf::fill_reg_map(arch, has_feature, target, &mut map);
|
|
map
|
|
}
|
|
}
|
|
}
|
|
|
|
#[derive(
|
|
Copy,
|
|
Clone,
|
|
Encodable,
|
|
Decodable,
|
|
Debug,
|
|
Eq,
|
|
PartialEq,
|
|
PartialOrd,
|
|
Hash,
|
|
HashStable_Generic
|
|
)]
|
|
pub enum InlineAsmClobberAbi {
|
|
X86,
|
|
X86_64Win,
|
|
X86_64SysV,
|
|
Arm,
|
|
AArch64,
|
|
RiscV,
|
|
}
|
|
|
|
impl InlineAsmClobberAbi {
|
|
/// Parses a clobber ABI for the given target, or returns a list of supported
|
|
/// clobber ABIs for the target.
|
|
pub fn parse(
|
|
arch: InlineAsmArch,
|
|
target: &Target,
|
|
name: Symbol,
|
|
) -> Result<Self, &'static [&'static str]> {
|
|
let name = &*name.as_str();
|
|
match arch {
|
|
InlineAsmArch::X86 => match name {
|
|
"C" | "system" | "efiapi" | "cdecl" | "stdcall" | "fastcall" => {
|
|
Ok(InlineAsmClobberAbi::X86)
|
|
}
|
|
_ => Err(&["C", "system", "efiapi", "cdecl", "stdcall", "fastcall"]),
|
|
},
|
|
InlineAsmArch::X86_64 => match name {
|
|
"C" | "system" if !target.is_like_windows => Ok(InlineAsmClobberAbi::X86_64SysV),
|
|
"C" | "system" if target.is_like_windows => Ok(InlineAsmClobberAbi::X86_64Win),
|
|
"win64" | "efiapi" => Ok(InlineAsmClobberAbi::X86_64Win),
|
|
"sysv64" => Ok(InlineAsmClobberAbi::X86_64SysV),
|
|
_ => Err(&["C", "system", "efiapi", "win64", "sysv64"]),
|
|
},
|
|
InlineAsmArch::Arm => match name {
|
|
"C" | "system" | "efiapi" | "aapcs" => Ok(InlineAsmClobberAbi::Arm),
|
|
_ => Err(&["C", "system", "efiapi", "aapcs"]),
|
|
},
|
|
InlineAsmArch::AArch64 => match name {
|
|
"C" | "system" | "efiapi" => Ok(InlineAsmClobberAbi::AArch64),
|
|
_ => Err(&["C", "system", "efiapi"]),
|
|
},
|
|
InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => match name {
|
|
"C" | "system" | "efiapi" => Ok(InlineAsmClobberAbi::RiscV),
|
|
_ => Err(&["C", "system", "efiapi"]),
|
|
},
|
|
_ => Err(&[]),
|
|
}
|
|
}
|
|
|
|
/// Returns the set of registers which are clobbered by this ABI.
|
|
pub fn clobbered_regs(self) -> &'static [InlineAsmReg] {
|
|
macro_rules! clobbered_regs {
|
|
($arch:ident $arch_reg:ident {
|
|
$(
|
|
$reg:ident,
|
|
)*
|
|
}) => {
|
|
&[
|
|
$(InlineAsmReg::$arch($arch_reg::$reg),)*
|
|
]
|
|
};
|
|
}
|
|
match self {
|
|
InlineAsmClobberAbi::X86 => clobbered_regs! {
|
|
X86 X86InlineAsmReg {
|
|
ax, cx, dx,
|
|
|
|
xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
|
|
|
|
k1, k2, k3, k4, k5, k6, k7,
|
|
|
|
mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7,
|
|
st0, st1, st2, st3, st4, st5, st6, st7,
|
|
}
|
|
},
|
|
InlineAsmClobberAbi::X86_64SysV => clobbered_regs! {
|
|
X86 X86InlineAsmReg {
|
|
ax, cx, dx, si, di, r8, r9, r10, r11,
|
|
|
|
xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
|
|
xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15,
|
|
zmm16, zmm17, zmm18, zmm19, zmm20, zmm21, zmm22, zmm23,
|
|
zmm24, zmm25, zmm26, zmm27, zmm28, zmm29, zmm30, zmm31,
|
|
|
|
k1, k2, k3, k4, k5, k6, k7,
|
|
|
|
mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7,
|
|
st0, st1, st2, st3, st4, st5, st6, st7,
|
|
}
|
|
},
|
|
InlineAsmClobberAbi::X86_64Win => clobbered_regs! {
|
|
X86 X86InlineAsmReg {
|
|
// rdi and rsi are callee-saved on windows
|
|
ax, cx, dx, r8, r9, r10, r11,
|
|
|
|
// xmm6-xmm15 are callee-saved on windows, but we need to
|
|
// mark them as clobbered anyways because the upper portions
|
|
// of ymm6-ymm15 are volatile.
|
|
xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7,
|
|
xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15,
|
|
zmm16, zmm17, zmm18, zmm19, zmm20, zmm21, zmm22, zmm23,
|
|
zmm24, zmm25, zmm26, zmm27, zmm28, zmm29, zmm30, zmm31,
|
|
|
|
k1, k2, k3, k4, k5, k6, k7,
|
|
|
|
mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7,
|
|
st0, st1, st2, st3, st4, st5, st6, st7,
|
|
}
|
|
},
|
|
InlineAsmClobberAbi::AArch64 => clobbered_regs! {
|
|
AArch64 AArch64InlineAsmReg {
|
|
x0, x1, x2, x3, x4, x5, x6, x7,
|
|
x8, x9, x10, x11, x12, x13, x14, x15,
|
|
// x18 is platform-reserved or temporary, but we exclude it
|
|
// here since it is a reserved register.
|
|
x16, x17, x30,
|
|
|
|
// Technically the low 64 bits of v8-v15 are preserved, but
|
|
// we have no way of expressing this using clobbers.
|
|
v0, v1, v2, v3, v4, v5, v6, v7,
|
|
v8, v9, v10, v11, v12, v13, v14, v15,
|
|
v16, v17, v18, v19, v20, v21, v22, v23,
|
|
v24, v25, v26, v27, v28, v29, v30, v31,
|
|
|
|
p0, p1, p2, p3, p4, p5, p6, p7,
|
|
p8, p9, p10, p11, p12, p13, p14, p15,
|
|
ffr,
|
|
|
|
}
|
|
},
|
|
InlineAsmClobberAbi::Arm => clobbered_regs! {
|
|
Arm ArmInlineAsmReg {
|
|
// r9 is platform-reserved and is treated as callee-saved.
|
|
r0, r1, r2, r3, r12, r14,
|
|
|
|
// The finest-grained register variant is used here so that
|
|
// partial uses of larger registers are properly handled.
|
|
s0, s1, s2, s3, s4, s5, s6, s7,
|
|
s8, s9, s10, s11, s12, s13, s14, s15,
|
|
// s16-s31 are callee-saved
|
|
d16, d17, d18, d19, d20, d21, d22, d23,
|
|
d24, d25, d26, d27, d28, d29, d30, d31,
|
|
}
|
|
},
|
|
InlineAsmClobberAbi::RiscV => clobbered_regs! {
|
|
RiscV RiscVInlineAsmReg {
|
|
// ra
|
|
x1,
|
|
// t0-t2
|
|
x5, x6, x7,
|
|
// a0-a7
|
|
x10, x11, x12, x13, x14, x15, x16, x17,
|
|
// t3-t6
|
|
x28, x29, x30, x31,
|
|
// ft0-ft7
|
|
f0, f1, f2, f3, f4, f5, f6, f7,
|
|
// fa0-fa7
|
|
f10, f11, f12, f13, f14, f15, f16, f17,
|
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// ft8-ft11
|
|
f28, f29, f30, f31,
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|
|
|
v0, v1, v2, v3, v4, v5, v6, v7,
|
|
v8, v9, v10, v11, v12, v13, v14, v15,
|
|
v16, v17, v18, v19, v20, v21, v22, v23,
|
|
v24, v25, v26, v27, v28, v29, v30, v31,
|
|
}
|
|
},
|
|
}
|
|
}
|
|
}
|