1aa01927d3
Support input/output in vector registers of PowerPC inline assembly This extends currently clobber-only vector registers (`vreg`) support to allow passing `#[repr(simd)]` types as input/output. | Architecture | Register class | Target feature | Allowed types | | ------------ | -------------- | -------------- | -------------- | | PowerPC | `vreg` | `altivec` | `i8x16`, `i16x8`, `i32x4`, `f32x4` | | PowerPC | `vreg` | `vsx` | `f32`, `f64`, `i64x2`, `f64x2` | In addition to floats and `core::simd` types listed above, `core::arch` types and custom `#[repr(simd)]` types of the same size and type are also allowed. All allowed types and relevant target features are currently unstable. r? `@Amanieu` `@rustbot` label +O-PowerPC +A-inline-assembly |
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| src | ||
| Cargo.toml | ||
| messages.ftl | ||
| README.md | ||
The codegen crate contains the code to convert from MIR into LLVM IR,
and then from LLVM IR into machine code. In general it contains code
that runs towards the end of the compilation process.
For more information about how codegen works, see the rustc dev guide.