Commit graph

1774 commits

Author SHA1 Message Date
bors
49e5e4e3a5 Auto merge of #140043 - ChrisDenton:rollup-vwf0s9j, r=ChrisDenton
Rollup of 8 pull requests

Successful merges:

 - #138934 (support config extensions)
 - #139091 (Rewrite on_unimplemented format string parser.)
 - #139753 (Make `#[naked]` an unsafe attribute)
 - #139762 (Don't assemble non-env/bound candidates if projection is rigid)
 - #139834 (Don't canonicalize crate paths)
 - #139868 (Move `pal::env` to `std::sys::env_consts`)
 - #139978 (Add citool command for generating a test dashboard)
 - #139995 (Clean UI tests 4 of n)

r? `@ghost`
`@rustbot` modify labels: rollup
2025-04-20 02:08:02 +00:00
Chris Denton
709f4fee50
Rollup merge of #139868 - thaliaarchi:move-env-consts-pal, r=joboet
Move `pal::env` to `std::sys::env_consts`

Combine the `std::env::consts` platform implementations as a single file. Use the Unix file as the base, since it has 28 entries, and fold the 8 singleton platforms into it. The Unix file was roughly grouped into Linux, Apple, BSD, and everything else, roughly in alphabetical order. Alphabetically order them to make it easier to maintain and discard the Unix-specific groups to generalize it to all platforms.

I'd prefer to have no fallback implementation, as I consider it a bug; however TEEOS, Trusty, and Xous have no definitions here. Since they otherwise have `pal` abstractions, that indicates that there are several platforms without `pal` abstractions which are also missing here. To support unsupported, create a little macro to handle the fallback case and not introduce ordering between the `cfg`s like `cfg_if!`.

I've named the module `std::sys::env_consts`, because they are used in `std::env::consts` and I intend to use the name `std::sys::env` for the combination of `Args` and `Vars`.

cc `@joboet` `@ChrisDenton`

Tracked in #117276.
2025-04-19 15:09:35 +00:00
Thalia Archibald
93fa96cfba Use struct update syntax for some TargetOptions 2025-04-18 19:49:23 -07:00
roblabla
1b39302571 Disable has_thread_local on i686-win7-windows-msvc
On Windows 7 32-bit, the alignment characteristic of the TLS Directory
don't appear to be respected by the PE Loader, leading to crashes. As
a result, let's disable has_thread_local to make sure TLS goes through
the emulation layer.
2025-04-18 13:30:26 +02:00
bors
15c4ccef03 Auto merge of #139940 - matthiaskrgr:rollup-rd4d3fn, r=matthiaskrgr
Rollup of 9 pull requests

Successful merges:

 - #135340 (Add `explicit_extern_abis` Feature and Enforce Explicit ABIs)
 - #139440 (rustc_target: RISC-V: feature addition batch 2)
 - #139667 (cfi: Remove #[no_sanitize(cfi)] for extern weak functions)
 - #139828 (Don't require rigid alias's trait to hold)
 - #139854 (Improve parse errors for stray lifetimes in type position)
 - #139889 (Clean UI tests 3 of n)
 - #139894 (Fix `opt-dist` CLI flag and make it work without LLD)
 - #139900 (stepping into impls for normalization is unproductive)
 - #139915 (replace some #[rustc_intrinsic] usage with use of the libcore declarations)

r? `@ghost`
`@rustbot` modify labels: rollup
2025-04-17 04:52:34 +00:00
Tsukasa OI
52392ec9e1 rustc_target: Use "B" shorthand on the RISC-V Android target
The "B" extension is ratified as a combination of three extensions: "Zba",
"Zbb" and "Zbs".  To maximize discoverability of the RISC-V target features,
this commit makes use of the "B" extension instead of its three members.

This way, `#[cfg(target_feature = "b")]` can also be used instead of:
`#[cfg(all(target_feature = "zba", target_feature = "zbb", target_feature = "zbs"))]`
2025-04-16 01:20:54 +00:00
Tsukasa OI
b084603c63 rustc_target: RISC-V: feature addition batch 2
This commit adds unprivileged ratified extensions that are either
dicoverable from the `riscv_hwprobe` syscall of the Linux kernel (as of
version 6.14) plus 1 minus 3 extensions.

Plus 1:

*   "B"
    This is a combination of "Zba", "Zbb" and "Zbs".
    Note:
    Although not required by the RISC-V specification, it is convenient to
    imply "B" from its three members (will be implemented in LLVM 21/22) but
    this is not yet implemented in Rust due to current implication handling.
    It still implies three members *from* "B".

Minus 2:

*   "Zcf" (target_arch = "riscv32" only)
    This is the compression instruction subset corresponding "F".
    This is implied from RV32 + "C" + "F" but this complex handling is
    not yet supported by Rust's feature handling.
*   "Zcd"
    This is the compression instruction subset corresponding "D".
    This is implied from "C" + "D" but this complex handling is
    not yet supported by Rust's feature handling.
*   "Supm"
    Unlike regular RISC-V extensions, "Supm" and "Sspm" extensions do not
    provide any specific architectural features / constraints but requires
    *some* mechanisms to control pointer masking for the current mode.
    For instance, reported existence of the "Supm" extension in Linux means
    that `prctl` system call to control pointer masking is available and
    there are alternative ways to detect the existence.

Notes:

*   Because this commit adds the "Zca" extension (an integer subset of the
    "C" extension), the "C" extension is modified to imply "Zca".
2025-04-16 01:20:54 +00:00
Tim Newsome
ac4014bd20 Add minimal x86_64-lynx-lynxos178 support.
It's possible to build no_std programs with this compiler.

> A tier 3 target must have a designated developer or developers (the "target
maintainers") on record to be CCed when issues arise regarding the target. (The
mechanism to track and CC such developers may evolve over time.)

Tim Newsome (@tnewsome-lynx) will be the designated developer for
x86_64-lynx-lynxos178 support.

> Targets must use naming consistent with any existing targets; for instance, a
target for the same CPU or OS as an existing Rust target should use the same
name for that CPU or OS. Targets should normally use the same names and naming
conventions as used elsewhere in the broader ecosystem beyond Rust (such as in
other toolchains), unless they have a very good reason to diverge. Changing the
name of a target can be highly disruptive, especially once the target reaches a
higher tier, so getting the name right is important even for a tier 3 target.

I believe the target is named appropriately.

> Target names should not introduce undue confusion or ambiguity unless
absolutely necessary to maintain ecosystem compatibility. For example, if the
name of the target makes people extremely likely to form incorrect beliefs about
what it targets, the name should be changed or augmented to disambiguate it.

The target name is not confusing.

> If possible, use only letters, numbers, dashes and underscores for the name.
Periods (.) are known to cause issues in Cargo.

Done.

> Tier 3 targets may have unusual requirements to build or use, but must not
create legal issues or impose onerous legal terms for the Rust project or for
Rust developers or users.
> The target must not introduce license incompatibilities.
> Anything added to the Rust repository must be under the standard Rust license
(MIT OR Apache-2.0).

All this new code is licensed under the Apache-2.0 license.

> The target must not cause the Rust tools or libraries built for any other host
(even when supporting cross-compilation to the target) to depend on any new
dependency less permissive than the Rust licensing policy. This applies whether
the dependency is a Rust crate that would require adding new license exceptions
(as specified by the tidy tool in the rust-lang/rust repository), or whether the
dependency is a native library or binary. In other words, the introduction of
the target must not cause a user installing or running a version of Rust or the
Rust tools to be subject to any new license requirements.

Done.

> Compiling, linking, and emitting functional binaries, libraries, or other code
for the target (whether hosted on the target itself or cross-compiling from
another target) must not depend on proprietary (non-FOSS) libraries. Host tools
built for the target itself may depend on the ordinary runtime libraries
supplied by the platform and commonly used by other applications built for the
target, but those libraries must not be required for code generation for the
target; cross-compilation to the target must not require such libraries at all.
For instance, rustc built for the target may depend on a common proprietary C
runtime library or console output library, but must not depend on a proprietary
code generation library or code optimization library. Rust's license permits
such combinations, but the Rust project has no interest in maintaining such
combinations within the scope of Rust itself, even at tier 3.

I think we're in the clear here. We do link against some static libraries that
are proprietary (like libm and libc), but those are not used to generate code.
E.g. the VxWorks target requires `wr-c++` to be installed, which is not
publically available.

> "onerous" here is an intentionally subjective term. At a minimum, "onerous"
legal/licensing terms include but are not limited to: non-disclosure
requirements, non-compete requirements, contributor license agreements (CLAs) or
equivalent, "non-commercial"/"research-only"/etc terms, requirements conditional
on the employer or employment of any particular Rust developers, revocable
terms, any requirements that create liability for the Rust project or its
developers or users, or any requirements that adversely affect the livelihood or
prospects of the Rust project or its developers or users.

Our intention is to allow anyone with access to LynxOS CDK to use Rust for it.

> Neither this policy nor any decisions made regarding targets shall create any
binding agreement or estoppel by any party. If any member of an approving Rust
team serves as one of the maintainers of a target, or has any legal or
employment requirement (explicit or implicit) that might affect their decisions
regarding a target, they must recuse themselves from any approval decisions
regarding the target's tier status, though they may otherwise participate in
discussions.
> This requirement does not prevent part or all of this policy from being cited
in an explicit contract or work agreement (e.g. to implement or maintain support
for a target). This requirement exists to ensure that a developer or team
responsible for reviewing and approving a target does not face any legal threats
or obligations that would prevent them from freely exercising their judgment in
such approval, even if such judgment involves subjective matters or goes beyond
the letter of these requirements.

No problem.

> Tier 3 targets should attempt to implement as much of the standard libraries
as possible and appropriate (core for most targets, alloc for targets that can
support dynamic memory allocation, std for targets with an operating system or
equivalent layer of system-provided functionality), but may leave some code
unimplemented (either unavailable or stubbed out as appropriate), whether
because the target makes it impossible to implement or challenging to implement.
The authors of pull requests are not obligated to avoid calling any portions of
the standard library on the basis of a tier 3 target not implementing those
portions.

With this first PR, only core is supported. I am working on support for the std
library and intend to submit that once all the tests are passing.

> The target must provide documentation for the Rust community explaining how to
build for the target, using cross-compilation if possible. If the target
supports running binaries, or running tests (even if they do not pass), the
documentation must explain how to run such binaries or tests for the target,
using emulation if possible or dedicated hardware if necessary.

This is documented in `src/doc/rustc/src/platform-support/lynxos_178.md`.

> Tier 3 targets must not impose burden on the authors of pull requests, or
other developers in the community, to maintain the target. In particular, do not
post comments (automated or manual) on a PR that derail or suggest a block on
the PR based on a tier 3 target. Do not send automated messages or notifications
(via any medium, including via @) to a PR author or others involved with a PR
regarding a tier 3 target, unless they have opted into such messages.
> Backlinks such as those generated by the issue/PR tracker when linking to an
issue or PR are not considered a violation of this policy, within reason.
However, such messages (even on a separate repository) must not generate
notifications to anyone involved with a PR who has not requested such
notifications.

Understood.

> Patches adding or updating tier 3 targets must not break any existing tier 2
or tier 1 target, and must not knowingly break another tier 3 target without
approval of either the compiler team or the maintainers of the other tier 3
target.
> In particular, this may come up when working on closely related targets, such
as variations of the same architecture with different features. Avoid
introducing unconditional uses of features that another variation of the target
may not have; use conditional compilation or runtime detection, as appropriate,
to let each target run code supported by that target.

As far as I know this change does not affect any other targets.

> Tier 3 targets must be able to produce assembly using at least one of rustc's
supported backends from any host target. (Having support in a fork of the
backend is not sufficient, it must be upstream.)

Many targets produce assembly for x86_64 so that also works for LynxOS-178.
2025-04-10 13:37:49 +02:00
Skgland
5eb535c568
remove compiler support for extern "rust-intrinsic" blocks 2025-04-06 21:32:58 +02:00
bors
f5c510260b Auto merge of #138947 - madsmtm:refactor-apple-versions, r=Noratrieb
Refactor Apple version handling in the compiler

Move various Apple version handling code in the compiler out `rustc_codegen_ssa` and into a place where it can be accessed by `rustc_attr_parsing`, which I found to be necessary when doing https://github.com/rust-lang/rust/pull/136867. Thought I'd split it out to make it easier to land, and to make further changes like https://github.com/rust-lang/rust/pull/131477 have fewer conflicts / PR dependencies.

There should be no functional changes in this PR.

`@rustbot` label O-apple
r? rust-lang/compiler
2025-04-06 10:16:28 +00:00
Stuart Cook
6907e011e4
Rollup merge of #139285 - tshepang:uniform-case, r=jieyouxu
use lower case to match other error messages
2025-04-05 13:18:16 +11:00
bors
5337252b99 Auto merge of #137869 - Noratrieb:Now_I_am_become_death,_the_destroyer_of_i686-pc-windows-gnu, r=workingjubilee
Demote i686-pc-windows-gnu to Tier 2

In accordance with [RFC 3771](https://github.com/rust-lang/rfcs/pull/3771). FCP has been completed.

tracking issue #138422

I also added a stub doc page for the target and renamed the windows-gnullvm page for consistency.
2025-04-04 15:45:03 +00:00
Mads Marquart
7e4379c4eb refactor: Move env parsing of deployment target to rustc_session 2025-04-04 15:02:22 +02:00
Mads Marquart
d74ce25b65 refactor: Move Apple OSVersion (back) to rustc_target
Also convert OSVersion into a proper struct for better type-safety.
2025-04-04 15:01:27 +02:00
Matthias Krüger
66e61c78e7
Rollup merge of #138949 - madsmtm:rename-to-darwin, r=WaffleLapkin
Rename `is_like_osx` to `is_like_darwin`

Replace `is_like_osx` with `is_like_darwin`, which more closely describes reality (OS X is the pre-2016 name for macOS, and is by now quite outdated; Darwin is the overall name for the OS underlying Apple's macOS, iOS, etc.).

``@rustbot`` label O-apple
r? compiler
2025-04-04 08:02:05 +02:00
Tshepang Mbambo
5c2a32296d use lower case to match other error messages 2025-04-03 01:07:55 +02:00
Noratrieb
6a1f57d095 Demote i686-pc-windows-gnu to Tier 2
In accordance with RFC 3771.

I also added a stub doc page for the target and renamed the
windows-gnullvm page for consistency.
2025-04-02 21:40:58 +02:00
Stuart Cook
6aec7de700
Rollup merge of #138823 - a4lg:riscv-feature-addition-base-i, r=Amanieu
rustc_target: RISC-V: add base `I`-related important extensions

Of ratified RISC-V features defined, this commit adds extensions satisfying following criteria:

*   Formerly a part of the `I` extension and splitted thereafter (now ratified as `I` + `Zifencei` + `Zicsr` + `Zicntr` + `Zihpm`) or
*   Dicoverable from newer versions of the Linux kernel and implemented as a part of `std_detect`'s feature (`Zihintpause`) and
*   Available on LLVM 18.

This is based on [the latest ratified ISA Manuals (version 20240411)](16154769/RISC-V+Technical+Specifications).

LLVM Definitions:

*   [`Zifencei`](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L133-L137)
*   [`Zicsr`](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L116-L120)
*   [`Zicntr`](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L122-L124)
*   [`Zihpm`](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L153-L155)
*   [`Zihintpause`](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L139-L144)

Additional (1):
One of those, `Zicsr`, is a dependency of many other ISA extensions and this commit adds correct dependencies to `Zicsr`.

Additional (2):
In RISC-V, `G` is an abbreviation of following extensions:
*   `I`
*   `M`
*   `A`
*   `F`
*   `D`
*   `Zicsr` (although implied by `F`)
*   `Zifencei`

and all RISC-V targets with the `G` abbreviation and targets for Android / VxWorks are updated accordingly.

Note:

Android will require RVA22 (likely RVA22U64) and some more extensions, which is a superset of RV64GC.  For VxWorks, all BSPs currently distributed by Wind River are for boards with RV64GC (this commit also updates `riscv32-wrs-vxworks` though).

--------

This is the version 4.
`Ztso` in the original proposal is removed on the PR version 2 due to the minimum LLVM version (non-experimental `Ztso` requires LLVM 19 while minimum LLVM version of Rust is 18). This is not back in PR version 3 and 4 after noticing adding `Ztso` is possible by checking host LLVM version because PR version 3 introduces compiler target changes (and adding more extensions would complicate the problems; sorry `Zihintpause`).

Version 4:
*   Fixed some commit messages,
*   Added Android / VxWorks targets to imply `G` and
*   Added an implication from `Zve32x` to `Zicsr` (which makes all vector extension subsets to imply `Zicsr`)
    since #138742 is now merged.

Related:
*   #44839
    (`riscv_target_feature`)
*   #114544
    (This PR can be a prerequisite of resolving a part of that tracking issue)
*   #138742
    (Touches the same place and vector extensions depend on `Zicsr`)

NOT Related but linked:
*   #132618
    (This PR won't be blocked by this issue since none of those extensions do not change the ABI)

`@rustbot` r? `@Amanieu`
`@rustbot` label +T-compiler +O-riscv +A-target-feature
2025-04-02 13:10:37 +11:00
Stuart Cook
5b0f658922
Rollup merge of #138003 - sayantn:new-amx, r=Amanieu
Add the new `amx` target features and the `movrs` target feature

Adds 5 new `amx` target features included in LLVM20. These are guarded under `x86_amx_intrinsics` (#126622)

 - `amx-avx512`
 - `amx-fp8`
 - `amx-movrs`
 - `amx-tf32`
 - `amx-transpose`

Adds the `movrs` target feature (from #137976).

`@rustbot` label O-x86_64 O-x86_32 T-compiler A-target-feature
r? `@Amanieu`
2025-04-02 13:10:36 +11:00
Tsukasa OI
6f40f0cdab rustc_target: RISC-V: add base "I"-related important extensions
Of ratified RISC-V features defined, this commit adds extensions
satisfying following criteria:

*   Formerly a part of the "I" extension and splitted thereafter
    (now ratified as "I" + "Zifencei" + "Zicsr" + "Zicntr" + "Zihpm") or
*   Dicoverable from newer versions of the Linux kernel and implemented
    as a part of std_detect's feature ("Zihintpause").

This is based on the latest ratified ISA Manuals (version 20240411).

Additional (1):

One of those, "Zicsr", is a dependency of many other ISA extensions and
this commit adds correct dependencies to "Zicsr".

Additional (2):

In RISC-V, "G" is an abbreviation of following extensions:

*   "I"
*   "M"
*   "A"
*   "F"
*   "D"
*   "Zicsr" (although implied by "F")
*   "Zifencei"

and all RISC-V targets with the "G" abbreviation and targets for Android /
VxWorks are updated accordingly.

Note:

Android will require RVA22 (likely RVA22U64) and some more extensions,
which is a superset of RV64GC.  For VxWorks, all BSPs currently distributed
by Wind River are for boards with RV64GC (this commit also updates
riscv32-wrs-vxworks though).
2025-04-02 01:13:40 +00:00
Matthias Krüger
32574153d9
Rollup merge of #138426 - madsmtm:vita-llvm-target, r=jieyouxu
Fix `armv7-sony-vita-newlibeabihf` LLVM target triple

It was previously normalized by LLVM to `thumbv7a-vita-unknown-eabihf` (can be seen with `clang -target thumbv7a-vita-eabihf -v`), which seems wrong, as Vita is the OS name.

Motivation: To make it easier to verify that [`cc-rs`' conversion from `rustc` to Clang/LLVM triples](https://github.com/rust-lang/cc-rs/issues/1431) is correct.

CC target maintainers ``@nikarh,`` ``@pheki`` and ``@ZetaNumbers.``
r? jieyouxu
2025-03-31 23:05:43 +02:00
bors
b9ea82b84a Auto merge of #137836 - madsmtm:openwrt-target-vendor, r=jieyouxu
Set `target_vendor = "openwrt"` on `mips64-openwrt-linux-musl`

OpenWRT is a Linux distribution for embedded network devices. The target name contains `openwrt`, so we should set `cfg(target_vendor = "openwrt")`.

This is similar to what other Linux distributions do (the only one in-tree is `x86_64-unikraft-linux-musl`, but that sets `target_vendor = "unikraft"`).

Motivation: To make correctly [parsing target names](https://github.com/rust-lang/cc-rs/pull/1413) simpler.

Fixes https://github.com/rust-lang/rust/issues/131165.

CC target maintainer `@Itus-Shield`
2025-03-30 08:33:29 +00:00
bors
85f518ec8e Auto merge of #138742 - taiki-e:riscv-vector, r=Amanieu
rustc_target: Add more RISC-V vector-related features and use zvl*b target features in vector ABI check

Currently, we have only unstable `v` target feature, but RISC-V have more vector-related extensions. The first commit of this PR adds them to unstable `riscv_target_feature`.

- `unaligned-vector-mem`: Has reasonably performant unaligned vector
  - [LLVM definition](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L1379)
  - Similar to currently unstable `unaligned-scalar-mem` target feature, but for vector instructions.
- `zvfh`: Vector Extension for Half-Precision Floating-Point
  - [ISA Manual](https://github.com/riscv/riscv-isa-manual/blob/riscv-isa-release-2336fdc-2025-03-19/src/v-st-ext.adoc#zvfh-vector-extension-for-half-precision-floating-point)
  - [LLVM definition](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L668)
  - This implies `zvfhmin` and `zfhmin`
- `zvfhmin`: Vector Extension for Minimal Half-Precision Floating-Point
  - [ISA Manual](https://github.com/riscv/riscv-isa-manual/blob/riscv-isa-release-2336fdc-2025-03-19/src/v-st-ext.adoc#zvfhmin-vector-extension-for-minimal-half-precision-floating-point)
  - [LLVM definition](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L662)
  - This implies `zve32f`
- `zve32x`, `zve32f`, `zve64x`, `zve64f`, `zve64d`: Vector Extensions for Embedded Processors
  - [ISA Manual](https://github.com/riscv/riscv-isa-manual/blob/riscv-isa-release-2336fdc-2025-03-19/src/v-st-ext.adoc#zve-vector-extensions-for-embedded-processors)
  - [LLVM definitions](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L612-L641)
  - `zve32x` implies `zvl32b`
  - `zve32f` implies `zve32x` and `f`
  - `zve64x` implies `zve32x` and `zvl64b`
  - `zve64f` implies `zve32f` and `zve64x`
  - `zve64d` implies `zve64f` and `d`
  - `v` implies `zve64d`
- `zvl*b`: Minimum Vector Length Standard Extensions
  - [ISA Manual](https://github.com/riscv/riscv-isa-manual/blob/riscv-isa-release-2336fdc-2025-03-19/src/v-st-ext.adoc#zvl-minimum-vector-length-standard-extensions)
  - [LLVM definitions](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L600-L610)
  - `zvl{N}b` implies `zvl{N>>1}b`
  - `v` implies `zvl128b`
- Vector Cryptography and Bit-manipulation Extensions
  - [ISA Manual](https://github.com/riscv/riscv-isa-manual/blob/riscv-isa-release-2336fdc-2025-03-19/src/vector-crypto.adoc)
  - [LLVM definitions](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L679-L807)
  - `zvkb`: Vector Bit-manipulation used in Cryptography
    - This implies `zve32x`
  - `zvbb`: Vector basic bit-manipulation instructions
    - This implies `zvkb`
  - `zvbc`: Vector Carryless Multiplication
    - This implies `zve64x`
  - `zvkg`: Vector GCM instructions for Cryptography
    - This implies `zve32x`
  - `zvkned`: Vector AES Encryption & Decryption (Single Round)
    - This implies `zve32x`
  - `zvknha`: Vector SHA-2 (SHA-256 only))
    - This implies `zve32x`
  - `zvknhb`: Vector SHA-2 (SHA-256 and SHA-512)
    - This implies `zve64x`
    - This is superset of `zvknha`, but doesn't imply that feature at least in LLVM
  - `zvksed`: SM4 Block Cipher Instructions
    - This implies `zve32x`
  - `zvksh`: SM3 Hash Function Instructions
    - This implies `zve32x`
  - `zvkt`: Vector Data-Independent Execution Latency
    - Similar to already stabilized scalar cryptography extension `zkt`.
  - `zvkn`: Shorthand for 'Zvkned', 'Zvknhb', 'Zvkb', and 'Zvkt'
    - Similar to already stabilized scalar cryptography extension `zkn`.
  - `zvknc`: Shorthand for 'Zvkn' and 'Zvbc'
  - `zvkng`: shorthand for 'Zvkn' and 'Zvkg'
  - `zvks`: shorthand for 'Zvksed', 'Zvksh', 'Zvkb', and 'Zvkt'
    - Similar to already stabilized scalar cryptography extension `zks`.
  - `zvksc`: shorthand for 'Zvks' and 'Zvbc'
  - `zvksg`: shorthand for 'Zvks' and 'Zvkg'

Also, our vector ABI check wants `zvl*b` target features, the second commit of this PR updates vector ABI check to use them.

4e2b096ed6/compiler/rustc_target/src/target_features.rs (L707-L708)

---

r? `@Amanieu`

`@rustbot` label +O-riscv +A-target-feature
2025-03-30 02:21:56 +00:00
Matthias Krüger
2b0c2f7904
Rollup merge of #138431 - madsmtm:uclibc-llvm-target, r=jieyouxu
Fix `uclibc` LLVM target triples

`uclibc` is not an environment understood by LLVM, it is only a concept in Clang that can be selected with `-muclibc` (it affects which dynamic linker is passed to the static linker's `-dynamic-linker` flag).

In fact, using `uclibcgnueabi`/`uclibc` is actively harmful, as it prevents LLVM from seeing that the target is gnu-like; we should use `gnueabi`/`gnu` directly instead.

Motivation: To make it easier to verify that [`cc-rs`' conversion from `rustc` to Clang/LLVM triples](https://github.com/rust-lang/cc-rs/issues/1431) is correct.

**There are no target maintainers for these targets.** So I'll CC ``@lancethepants`` and ``@skrap`` who maintain the related `armv7-unknown-linux-uclibceabi` and `armv7-unknown-linux-uclibceabihf` (both of which already pass `-gnu` instead of `-uclibc`) in case they have any insights.

r? jieyouxu
2025-03-29 21:08:11 +01:00
bors
068609ce76 Auto merge of #138601 - RalfJung:wasm-abi-fcw, r=alexcrichton
add FCW to warn about wasm ABI transition

See https://github.com/rust-lang/rust/issues/122532 for context: the "C" ABI on wasm32-unk-unk will change. The goal of this lint is to warn about any function definition and calls whose behavior will be affected by the change. My understanding is the following:
- scalar arguments are fine
  - including 128 bit types, they get passed as two `i64` arguments in both ABIs
- `repr(C)` structs (recursively) wrapping a single scalar argument are fine (unless they have extra padding due to over-alignment attributes)
- all return values are fine

`@bjorn3` `@alexcrichton` `@Manishearth` is that correct?

I am making this a "show up in future compat reports" lint to maximize the chances people become aware of this. OTOH this likely means warnings for most users of Diplomat so maybe we shouldn't do this?

IIUC, wasm-bindgen should be unaffected by this lint as they only pass scalar types as arguments.

Tracking issue: https://github.com/rust-lang/rust/issues/138762
Transition plan blog post: https://github.com/rust-lang/blog.rust-lang.org/pull/1531

try-job: dist-various-2
2025-03-26 00:06:46 +00:00
Mads Marquart
328846c6eb Rename is_like_osx to is_like_darwin 2025-03-25 21:53:52 +01:00
Ralf Jung
072ccce553 make -Zwasm-c-abi=legacy suppress the lint 2025-03-25 08:22:35 +01:00
Ralf Jung
c961d123d2 add FCW to warn about wasm ABI transition 2025-03-25 08:22:35 +01:00
Takayuki Maeda
e9a528c9b5
Rollup merge of #138701 - tvladyslav:serializable_default_codegen_backend, r=workingjubilee
Make default_codegen_backend serializable

This PR makes default_codegen_backend serializable.
2025-03-25 15:36:33 +09:00
Ralf Jung
b2d7271858 target spec check: better error when llvm-floatabi is missing 2025-03-21 16:08:48 +01:00
Taiki Endo
8a6f96a4a0 rustc_target: Use zvl*b target features in vector ABI check 2025-03-20 19:48:02 +09:00
Taiki Endo
55add8fce3 rustc_target: Add more RISC-V vector-related features 2025-03-20 19:47:57 +09:00
Vladyslav Tsilytskyi
39efa7c590 Make default_codegen_backend serializable 2025-03-19 12:35:18 +01:00
Matthias Krüger
aa53a72dff
Rollup merge of #138608 - heiher:issue-116344, r=RalfJung
rustc_target: Add target feature constraints for LoongArch

Part of https://github.com/rust-lang/rust/issues/116344

r? `@RalfJung`
2025-03-17 22:49:07 +01:00
WANG Rui
0ee99cf240 rustc_target: Add target feature constraints for LoongArch
Part of https://github.com/rust-lang/rust/issues/116344
2025-03-17 22:45:35 +08:00
Jacob Pratt
b3b7a3b8d2
Rollup merge of #137621 - Berrysoft:cygwin-std, r=joboet
Add std support to cygwin target
2025-03-17 05:47:49 -04:00
León Orell Valerian Liehr
10055fb03a
Rollup merge of #138056 - heiher:loong64v1.1-features, r=petrochenkov
rustc_target: Add target features for LoongArch v1.1

This patch adds new target features for LoongArch v1.1:

* div32
* lam-bh
* lamcas
* ld-seq-sa
* scq
2025-03-15 00:18:22 +01:00
Jacob Pratt
459352a217
Rollup merge of #136892 - erickt:fuchsia-target, r=jieyouxu
Sync Fuchsia target spec with clang Fuchsia driver

This updates the Fuchsia target spec with the [Clang Fuchsia driver], which picks up a few changes:

* Adds `-z start-stop-visibility=hidden` and `-z rel` to the pre link arguments.
* Adds `--execute-only` and `--fix-cortex-a53-843419` for `aarch64-unknown-fuchsia`.
* Enables the equivalent cpu features for `x86-64-v2` for `x86_64-unknown-fuchsia`, which is our minimum supported x86_64 platform according to [RFC-0073].

try-job: x86_64-fuchsia

[Clang Fuchsia driver]: 8374d42186/clang/lib/Driver/ToolChains/Fuchsia.cpp
[RFC-0073]: https://fuchsia.dev/fuchsia-src/contribute/governance/rfcs/0073_x86_64_platform_requirement
2025-03-14 01:37:29 -04:00
WANG Rui
d989bf5bbe rustc_target: Add target features for LoongArch v1.1 2025-03-14 09:52:02 +08:00
Matthias Krüger
69b3ad18d2
Rollup merge of #138427 - madsmtm:vxworks-llvm-target, r=jieyouxu
Fix RISC-V VxWorks LLVM target triples

The targets `riscv32-wrs-vxworks` and `riscv64-wrs-vxworks` uses the plain `$ARCH` LLVM triple, which LLVM normalizes to `$ARCH-unknown-unknown`, we should use `$ARCH-unknown-linux-gnu$ABI` which is consistent with the the other VxWorks targets.

Motivation: To make it easier to verify that [`cc-rs`' conversion from `rustc` to Clang/LLVM triples](https://github.com/rust-lang/cc-rs/issues/1431) is correct.

Alternative: Pass `$ARCH-unknown-none` in the other VxWorks LLVM triples, I don't know anything about VxWorks, so am unsure which is the most correct option.

CC target maintainer `@biabbas.`
r? jieyouxu
2025-03-13 17:44:12 +01:00
Mads Marquart
eab700a0aa Fix uclibc LLVM target triples
`uclibc` is not an environment understood by LLVM, it is only a concept
in Clang that can be selected with `-muclibc` (it affects which dynamic
linker is passed to the static linker's `-dynamic-linker` flag).

In fact, using `uclibcgnueabi`/`uclibc` is actively harmful, as it
prevents LLVM from seeing that the target is gnu-like; we should use
`gnueabi`/`gnu` directly instead.
2025-03-12 23:40:25 +01:00
Mads Marquart
65bd61d2fb Fix armv7-sony-vita-newlibeabihf LLVM target triple
It was previously normalized by LLVM to `thumbv7a-vita-unknown-eabihf`,
which is probably wrong, as Vita is the OS.
2025-03-12 22:44:59 +01:00
Mads Marquart
0434013a6e Fix RISC-V VxWorks LLVM target triples
The targets used the plain `$ARCH` triple, which LLVM normalizes to
`$ARCH-unknown-unknown`, which is inconsistent with the the other
VxWorks targets which all use `$ARCH-unknown-linux-gnu$ABI`.
2025-03-12 22:42:17 +01:00
Matthias Krüger
d93ef397ce
Rollup merge of #138331 - nnethercote:use-RUSTC_LINT_FLAGS-more, r=onur-ozkan,jieyouxu
Use `RUSTC_LINT_FLAGS` more

An alternative to the failed #138084.

Fixes #138106.

r? ````@jieyouxu````
2025-03-12 17:59:08 +01:00
bors
ebf0cf75d3 Auto merge of #137586 - nnethercote:SetImpliedBits, r=bjorn3
Speed up target feature computation

The LLVM backend calls `LLVMRustHasFeature` twice for every feature. In short-running rustc invocations, this accounts for a surprising amount of work.

r? `@bjorn3`
2025-03-11 12:05:16 +00:00
Nicholas Nethercote
ff0a5fe975 Remove #![warn(unreachable_pub)] from all compiler/ crates.
It's no longer necessary now that `-Wunreachable_pub` is being passed.
2025-03-11 13:14:21 +11:00
Arjun Ramesh
336a327f7c Target definition for wasm32-wali-linux-musl to support the Wasm Linux
Interface

This commit does not patch libc, stdarch, or cc
2025-03-10 21:26:45 -04:00
王宇逸
886fb15c0f Update metadata for cygwin target 2025-03-10 21:23:31 +08:00
许杰友 Jieyou Xu (Joe)
063ef18fdc Revert "Use workspace lints for crates in compiler/ #138084"
Revert <https://github.com/rust-lang/rust/pull/138084> to buy time to
consider options that avoids breaking downstream usages of cargo on
distributed `rustc-src` artifacts, where such cargo invocations fail due
to inability to inherit `lints` from workspace root manifest's
`workspace.lints` (this is only valid for the source rust-lang/rust
workspace, but not really the distributed `rustc-src` artifacts).

This breakage was reported in
<https://github.com/rust-lang/rust/issues/138304>.

This reverts commit 48caf81484, reversing
changes made to c6662879b2.
2025-03-10 18:12:47 +08:00
Matthias Krüger
48caf81484
Rollup merge of #138084 - nnethercote:workspace-lints, r=jieyouxu
Use workspace lints for crates in `compiler/`

This is nicer and hopefully less error prone than specifying lints via bootstrap.

r? ``@jieyouxu``
2025-03-09 10:34:50 +01:00