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LLVM 16: Update RISCV data layout

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This commit is contained in:
Tim Neumann 2022-11-06 19:03:22 +00:00
parent 1e1e5b8d98
commit f414715ebf
7 changed files with 10 additions and 6 deletions
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4
compiler/rustc_codegen_llvm/src/context.rs
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@ -158,6 +158,10 @@ pub unsafe fn create_module<'ll>(
if sess.target.arch == "s390x" {
target_data_layout = target_data_layout.replace("-v128:64", "");
}
if sess.target.arch == "riscv64" {
target_data_layout = target_data_layout.replace("-n32:64-", "-n64-");
}
}
// Ensure the data-layout values hardcoded remain the defaults.