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Auto merge of #91813 - matthiaskrgr:rollup-nryyeyj, r=matthiaskrgr

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Rollup of 8 pull requests

Successful merges:

 - #90081 (Make `intrinsics::write_bytes` const)
 - #91643 (asm: Allow using r9 (ARM) and x18 (AArch64) if they are not reserved by the current target)
 - #91737 (Make certain panicky stdlib functions behave better under panic_immediate_abort)
 - #91750 (rustdoc: Add regression test for Iterator as notable trait on &T)
 - #91764 (Do not ICE when suggesting elided lifetimes on non-existent spans.)
 - #91780 (Remove hir::Node::hir_id.)
 - #91797 (Fix zero-sized reference to deallocated memory)
 - #91806 (Make `Unique`s methods `const`)

Failed merges:

r? `@ghost`
`@rustbot` modify labels: rollup
This commit is contained in:
bors 2021-12-12 00:58:30 +00:00
commit e70e4d499d
24 changed files with 289 additions and 92 deletions
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7
compiler/rustc_ast_lowering/src/asm.rs
View file

@ -64,7 +64,12 @@ impl<'a, 'hir> LoweringContext<'a, 'hir> {
let mut clobber_abis = FxHashMap::default();
if let Some(asm_arch) = asm_arch {
for (abi_name, abi_span) in &asm.clobber_abis {
match asm::InlineAsmClobberAbi::parse(asm_arch, &self.sess.target, *abi_name) {
match asm::InlineAsmClobberAbi::parse(
asm_arch,
|feature| self.sess.target_features.contains(&Symbol::intern(feature)),
&self.sess.target,
*abi_name,
) {
Ok(abi) => {
// If the abi was already in the list, emit an error
match clobber_abis.get(&abi) {

1
compiler/rustc_codegen_ssa/src/target_features.rs
View file

@ -36,6 +36,7 @@ const ARM_ALLOWED_FEATURES: &[(&str, Option<Symbol>)] = &[
// #[target_feature].
("thumb-mode", Some(sym::arm_target_feature)),
("thumb2", Some(sym::arm_target_feature)),
("reserve-r9", Some(sym::arm_target_feature)),
];
const AARCH64_ALLOWED_FEATURES: &[(&str, Option<Symbol>)] = &[

24
compiler/rustc_const_eval/src/interpret/intrinsics.rs
View file

@ -322,6 +322,9 @@ impl<'mir, 'tcx: 'mir, M: Machine<'mir, 'tcx>> InterpCx<'mir, 'tcx, M> {
sym::copy => {
self.copy_intrinsic(&args[0], &args[1], &args[2], /*nonoverlapping*/ false)?;
}
sym::write_bytes => {
self.write_bytes_intrinsic(&args[0], &args[1], &args[2])?;
}
sym::offset => {
let ptr = self.read_pointer(&args[0])?;
let offset_count = self.read_scalar(&args[1])?.to_machine_isize(self)?;
@ -567,6 +570,27 @@ impl<'mir, 'tcx: 'mir, M: Machine<'mir, 'tcx>> InterpCx<'mir, 'tcx, M> {
self.memory.copy(src, align, dst, align, size, nonoverlapping)
}
pub(crate) fn write_bytes_intrinsic(
&mut self,
dst: &OpTy<'tcx, <M as Machine<'mir, 'tcx>>::PointerTag>,
byte: &OpTy<'tcx, <M as Machine<'mir, 'tcx>>::PointerTag>,
count: &OpTy<'tcx, <M as Machine<'mir, 'tcx>>::PointerTag>,
) -> InterpResult<'tcx> {
let layout = self.layout_of(dst.layout.ty.builtin_deref(true).unwrap().ty)?;
let dst = self.read_pointer(&dst)?;
let byte = self.read_scalar(&byte)?.to_u8()?;
let count = self.read_scalar(&count)?.to_machine_usize(self)?;
let len = layout
.size
.checked_mul(count, self)
.ok_or_else(|| err_ub_format!("overflow computing total size of `write_bytes`"))?;
let bytes = std::iter::repeat(byte).take(len.bytes_usize());
self.memory.write_bytes(dst, bytes)
}
pub(crate) fn raw_eq_intrinsic(
&mut self,
lhs: &OpTy<'tcx, <M as Machine<'mir, 'tcx>>::PointerTag>,

28
compiler/rustc_hir/src/hir.rs
View file

@ -3210,34 +3210,6 @@ impl<'hir> Node<'hir> {
}
}
pub fn hir_id(&self) -> Option<HirId> {
match self {
Node::Item(Item { def_id, .. })
| Node::TraitItem(TraitItem { def_id, .. })
| Node::ImplItem(ImplItem { def_id, .. })
| Node::ForeignItem(ForeignItem { def_id, .. }) => Some(HirId::make_owner(*def_id)),
Node::Field(FieldDef { hir_id, .. })
| Node::AnonConst(AnonConst { hir_id, .. })
| Node::Expr(Expr { hir_id, .. })
| Node::Stmt(Stmt { hir_id, .. })
| Node::Ty(Ty { hir_id, .. })
| Node::Binding(Pat { hir_id, .. })
| Node::Pat(Pat { hir_id, .. })
| Node::Arm(Arm { hir_id, .. })
| Node::Block(Block { hir_id, .. })
| Node::Local(Local { hir_id, .. })
| Node::Lifetime(Lifetime { hir_id, .. })
| Node::Param(Param { hir_id, .. })
| Node::Infer(InferArg { hir_id, .. })
| Node::GenericParam(GenericParam { hir_id, .. }) => Some(*hir_id),
Node::TraitRef(TraitRef { hir_ref_id, .. }) => Some(*hir_ref_id),
Node::PathSegment(PathSegment { hir_id, .. }) => *hir_id,
Node::Variant(Variant { id, .. }) => Some(*id),
Node::Ctor(variant) => variant.ctor_hir_id(),
Node::Crate(_) | Node::Visibility(_) => None,
}
}
/// Returns `Constness::Const` when this node is a const fn/impl/item.
pub fn constness_for_typeck(&self) -> Constness {
match self {

21
compiler/rustc_lint/src/context.rs
View file

@ -22,9 +22,7 @@ use ast::util::unicode::TEXT_FLOW_CONTROL_CHARS;
use rustc_ast as ast;
use rustc_data_structures::fx::FxHashMap;
use rustc_data_structures::sync;
use rustc_errors::{
add_elided_lifetime_in_path_suggestion, struct_span_err, Applicability, SuggestionStyle,
};
use rustc_errors::{struct_span_err, Applicability, SuggestionStyle};
use rustc_hir as hir;
use rustc_hir::def::Res;
use rustc_hir::def_id::{CrateNum, DefId};
@ -670,23 +668,6 @@ pub trait LintContext: Sized {
) => {
db.span_note(span_def, "the macro is defined here");
}
BuiltinLintDiagnostics::ElidedLifetimesInPaths(
n,
path_span,
incl_angl_brckt,
insertion_span,
anon_lts,
) => {
add_elided_lifetime_in_path_suggestion(
sess.source_map(),
&mut db,
n,
path_span,
incl_angl_brckt,
insertion_span,
anon_lts,
);
}
BuiltinLintDiagnostics::UnknownCrateTypes(span, note, sugg) => {
db.span_suggestion(span, &note, sugg, Applicability::MaybeIncorrect);
}

1
compiler/rustc_lint_defs/src/lib.rs
View file

@ -289,7 +289,6 @@ pub enum BuiltinLintDiagnostics {
AbsPathWithModule(Span),
ProcMacroDeriveResolutionFallback(Span),
MacroExpandedMacroExportsAccessedByAbsolutePaths(Span),
ElidedLifetimesInPaths(usize, Span, bool, Span, String),
UnknownCrateTypes(Span, String, String),
UnusedImports(String, Vec<(Span, String)>),
RedundantImport(Vec<(Span, bool)>, Ident),

5
compiler/rustc_resolve/src/late/diagnostics.rs
View file

@ -2115,6 +2115,11 @@ impl<'tcx> LifetimeContext<'_, 'tcx> {
})
.map(|(formatter, span)| (*span, formatter(name)))
.collect();
if spans_suggs.is_empty() {
// If all the spans come from macros, we cannot extract snippets and then
// `formatters` only contains None and `spans_suggs` is empty.
return;
}
err.multipart_suggestion_verbose(
&format!(
"consider using the `{}` lifetime",

20
compiler/rustc_target/src/asm/aarch64.rs
View file

@ -1,4 +1,5 @@
use super::{InlineAsmArch, InlineAsmType};
use crate::spec::Target;
use rustc_macros::HashStable_Generic;
use std::fmt;
@ -70,6 +71,22 @@ impl AArch64InlineAsmRegClass {
}
}
pub fn reserved_x18(
_arch: InlineAsmArch,
_has_feature: impl FnMut(&str) -> bool,
target: &Target,
) -> Result<(), &'static str> {
if target.os == "android"
|| target.is_like_fuchsia
|| target.is_like_osx
|| target.is_like_windows
{
Err("x18 is a reserved register on this target")
} else {
Ok(())
}
}
def_regs! {
AArch64 AArch64InlineAsmReg AArch64InlineAsmRegClass {
x0: reg = ["x0", "w0"],
@ -90,6 +107,7 @@ def_regs! {
x15: reg = ["x15", "w15"],
x16: reg = ["x16", "w16"],
x17: reg = ["x17", "w17"],
x18: reg = ["x18", "w18"] % reserved_x18,
x20: reg = ["x20", "w20"],
x21: reg = ["x21", "w21"],
x22: reg = ["x22", "w22"],
@ -149,8 +167,6 @@ def_regs! {
p14: preg = ["p14"],
p15: preg = ["p15"],
ffr: preg = ["ffr"],
#error = ["x18", "w18"] =>
"x18 is used as a reserved register on some targets and cannot be used as an operand for inline asm",
#error = ["x19", "w19"] =>
"x19 is used internally by LLVM and cannot be used as an operand for inline asm",
#error = ["x29", "w29", "fp", "wfp"] =>

19
compiler/rustc_target/src/asm/arm.rs
View file

@ -99,6 +99,22 @@ fn not_thumb1(
}
}
fn reserved_r9(
arch: InlineAsmArch,
mut has_feature: impl FnMut(&str) -> bool,
target: &Target,
) -> Result<(), &'static str> {
not_thumb1(arch, &mut has_feature, target)?;
// We detect this using the reserved-r9 feature instead of using the target
// because the relocation model can be changed with compiler options.
if has_feature("reserved-r9") {
Err("the RWPI static base register (r9) cannot be used as an operand for inline asm")
} else {
Ok(())
}
}
def_regs! {
Arm ArmInlineAsmReg ArmInlineAsmRegClass {
r0: reg = ["r0", "a1"],
@ -109,6 +125,7 @@ def_regs! {
r5: reg = ["r5", "v2"],
r7: reg = ["r7", "v4"] % frame_pointer_r7,
r8: reg = ["r8", "v5"] % not_thumb1,
r9: reg = ["r9", "v6", "rfp"] % reserved_r9,
r10: reg = ["r10", "sl"] % not_thumb1,
r11: reg = ["r11", "fp"] % frame_pointer_r11,
r12: reg = ["r12", "ip"] % not_thumb1,
@ -195,8 +212,6 @@ def_regs! {
q15: qreg = ["q15"],
#error = ["r6", "v3"] =>
"r6 is used internally by LLVM and cannot be used as an operand for inline asm",
#error = ["r9", "v6", "rfp"] =>
"r9 is used internally by LLVM and cannot be used as an operand for inline asm",
#error = ["r13", "sp"] =>
"the stack pointer cannot be used as an operand for inline asm",
#error = ["r15", "pc"] =>

34
compiler/rustc_target/src/asm/mod.rs
View file

@ -785,6 +785,7 @@ pub enum InlineAsmClobberAbi {
X86_64SysV,
Arm,
AArch64,
AArch64NoX18,
RiscV,
}
@ -793,6 +794,7 @@ impl InlineAsmClobberAbi {
/// clobber ABIs for the target.
pub fn parse(
arch: InlineAsmArch,
has_feature: impl FnMut(&str) -> bool,
target: &Target,
name: Symbol,
) -> Result<Self, &'static [&'static str]> {
@ -816,7 +818,13 @@ impl InlineAsmClobberAbi {
_ => Err(&["C", "system", "efiapi", "aapcs"]),
},
InlineAsmArch::AArch64 => match name {
"C" | "system" | "efiapi" => Ok(InlineAsmClobberAbi::AArch64),
"C" | "system" | "efiapi" => {
Ok(if aarch64::reserved_x18(arch, has_feature, target).is_err() {
InlineAsmClobberAbi::AArch64NoX18
} else {
InlineAsmClobberAbi::AArch64
})
}
_ => Err(&["C", "system", "efiapi"]),
},
InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => match name {
@ -891,8 +899,25 @@ impl InlineAsmClobberAbi {
AArch64 AArch64InlineAsmReg {
x0, x1, x2, x3, x4, x5, x6, x7,
x8, x9, x10, x11, x12, x13, x14, x15,
// x18 is platform-reserved or temporary, but we exclude it
// here since it is a reserved register.
x16, x17, x18, x30,
// Technically the low 64 bits of v8-v15 are preserved, but
// we have no way of expressing this using clobbers.
v0, v1, v2, v3, v4, v5, v6, v7,
v8, v9, v10, v11, v12, v13, v14, v15,
v16, v17, v18, v19, v20, v21, v22, v23,
v24, v25, v26, v27, v28, v29, v30, v31,
p0, p1, p2, p3, p4, p5, p6, p7,
p8, p9, p10, p11, p12, p13, p14, p15,
ffr,
}
},
InlineAsmClobberAbi::AArch64NoX18 => clobbered_regs! {
AArch64 AArch64InlineAsmReg {
x0, x1, x2, x3, x4, x5, x6, x7,
x8, x9, x10, x11, x12, x13, x14, x15,
x16, x17, x30,
// Technically the low 64 bits of v8-v15 are preserved, but
@ -910,7 +935,8 @@ impl InlineAsmClobberAbi {
},
InlineAsmClobberAbi::Arm => clobbered_regs! {
Arm ArmInlineAsmReg {
// r9 is platform-reserved and is treated as callee-saved.
// r9 is either platform-reserved or callee-saved. Either
// way we don't need to clobber it.
r0, r1, r2, r3, r12, r14,
// The finest-grained register variant is used here so that