bjoernager/rust
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Merge commit 'c07d1e2f88' into sync_cg_clif-2023-10-21

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This commit is contained in:
bjorn3 2023-10-21 19:54:51 +00:00
commit e07f47b6c5
20 changed files with 163 additions and 493 deletions
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2
compiler/rustc_codegen_cranelift/src/debuginfo/mod.rs
View file

@ -20,7 +20,7 @@ use crate::prelude::*;
pub(crate) fn producer() -> String {
format!(
"cg_clif (rustc {}, cranelift {})",
"rustc version {} with cranelift {}",
rustc_interface::util::rustc_version_str().unwrap_or("unknown version"),
cranelift_codegen::VERSION,
)

47
compiler/rustc_codegen_cranelift/src/driver/aot.rs
View file

@ -394,28 +394,31 @@ pub(crate) fn run_aot(
let modules = tcx.sess.time("codegen mono items", || {
cgus.iter()
.enumerate()
.map(|(i, cgu)| match cgu_reuse[i] {
CguReuse::No => {
let dep_node = cgu.codegen_dep_node(tcx);
tcx.dep_graph
.with_task(
dep_node,
tcx,
(
backend_config.clone(),
global_asm_config.clone(),
cgu.name(),
concurrency_limiter.acquire(tcx.sess.diagnostic()),
),
module_codegen,
Some(rustc_middle::dep_graph::hash_result),
)
.0
}
CguReuse::PreLto => unreachable!("LTO not yet supported"),
CguReuse::PostLto => {
concurrency_limiter.job_already_done();
OngoingModuleCodegen::Sync(reuse_workproduct_for_cgu(tcx, cgu))
.map(|(i, cgu)| {
let cgu_reuse =
if backend_config.disable_incr_cache { CguReuse::No } else { cgu_reuse[i] };
match cgu_reuse {
CguReuse::No => {
let dep_node = cgu.codegen_dep_node(tcx);
tcx.dep_graph
.with_task(
dep_node,
tcx,
(
backend_config.clone(),
global_asm_config.clone(),
cgu.name(),
concurrency_limiter.acquire(tcx.sess.diagnostic()),
),
module_codegen,
Some(rustc_middle::dep_graph::hash_result),
)
.0
}
CguReuse::PreLto | CguReuse::PostLto => {
concurrency_limiter.job_already_done();
OngoingModuleCodegen::Sync(reuse_workproduct_for_cgu(tcx, cgu))
}
}
})
.collect::<Vec<_>>()

8
compiler/rustc_codegen_cranelift/src/global_asm.rs
View file

@ -81,6 +81,10 @@ pub(crate) fn codegen_global_asm_item(tcx: TyCtxt<'_>, global_asm: &mut String,
}
}
pub(crate) fn asm_supported(tcx: TyCtxt<'_>) -> bool {
cfg!(feature = "inline_asm") && !tcx.sess.target.is_like_windows
}
#[derive(Debug)]
pub(crate) struct GlobalAsmConfig {
asm_enabled: bool,
@ -90,10 +94,8 @@ pub(crate) struct GlobalAsmConfig {
impl GlobalAsmConfig {
pub(crate) fn new(tcx: TyCtxt<'_>) -> Self {
let asm_enabled = cfg!(feature = "inline_asm") && !tcx.sess.target.is_like_windows;
GlobalAsmConfig {
asm_enabled,
asm_enabled: asm_supported(tcx),
assembler: crate::toolchain::get_toolchain_binary(tcx.sess, "as"),
output_filenames: tcx.output_filenames(()).clone(),
}

59
compiler/rustc_codegen_cranelift/src/inline_asm.rs
View file

@ -8,6 +8,7 @@ use rustc_span::sym;
use rustc_target::asm::*;
use target_lexicon::BinaryFormat;
use crate::global_asm::asm_supported;
use crate::prelude::*;
enum CInlineAsmOperand<'tcx> {
@ -44,9 +45,13 @@ pub(crate) fn codegen_inline_asm<'tcx>(
) {
// FIXME add .eh_frame unwind info directives
if !template.is_empty()
&& (cfg!(not(feature = "inline_asm")) || fx.tcx.sess.target.is_like_windows)
{
if !asm_supported(fx.tcx) {
if template.is_empty() {
let destination_block = fx.get_block(destination.unwrap());
fx.bcx.ins().jump(destination_block, &[]);
return;
}
// Used by panic_abort
if template[0] == InlineAsmTemplatePiece::String("int $$0x29".to_string()) {
fx.bcx.ins().trap(TrapCode::User(1));
@ -144,6 +149,16 @@ pub(crate) fn codegen_inline_asm<'tcx>(
return;
}
// Used by core::hint::spin_loop()
if template[0]
== InlineAsmTemplatePiece::String(".insn i 0x0F, 0, x0, x0, 0x010".to_string())
&& template.len() == 1
{
let destination_block = fx.get_block(destination.unwrap());
fx.bcx.ins().jump(destination_block, &[]);
return;
}
// Used by measureme
if template[0] == InlineAsmTemplatePiece::String("xor %eax, %eax".to_string())
&& template[1] == InlineAsmTemplatePiece::String("\n".to_string())
@ -223,6 +238,16 @@ pub(crate) fn codegen_inline_asm<'tcx>(
fx.bcx.ins().jump(destination_block, &[]);
return;
}
if cfg!(not(feature = "inline_asm")) {
fx.tcx.sess.span_err(
span,
"asm! and global_asm! support is disabled while compiling rustc_codegen_cranelift",
);
} else {
fx.tcx.sess.span_err(span, "asm! and global_asm! are not yet supported on Windows");
}
return;
}
let operands = operands
@ -745,6 +770,13 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> {
// x19 is reserved by LLVM for the "base pointer", so rustc doesn't allow using it
generated_asm.push_str(" mov x19, x0\n");
}
InlineAsmArch::RiscV64 => {
generated_asm.push_str(" addi sp, sp, -16\n");
generated_asm.push_str(" sd ra, 8(sp)\n");
generated_asm.push_str(" sd s1, 0(sp)\n"); // s1 is callee saved
// s1/x9 is reserved by LLVM for the "base pointer", so rustc doesn't allow using it
generated_asm.push_str(" mv s1, a0\n");
}
_ => unimplemented!("prologue for {:?}", arch),
}
}
@ -761,6 +793,12 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> {
generated_asm.push_str(" ldp fp, lr, [sp], #32\n");
generated_asm.push_str(" ret\n");
}
InlineAsmArch::RiscV64 => {
generated_asm.push_str(" ld s1, 0(sp)\n");
generated_asm.push_str(" ld ra, 8(sp)\n");
generated_asm.push_str(" addi sp, sp, 16\n");
generated_asm.push_str(" ret\n");
}
_ => unimplemented!("epilogue for {:?}", arch),
}
}
@ -771,7 +809,10 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> {
generated_asm.push_str(" ud2\n");
}
InlineAsmArch::AArch64 => {
generated_asm.push_str(" brk #0x1");
generated_asm.push_str(" brk #0x1\n");
}
InlineAsmArch::RiscV64 => {
generated_asm.push_str(" ebreak\n");
}
_ => unimplemented!("epilogue_noreturn for {:?}", arch),
}
@ -794,6 +835,11 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> {
reg.emit(generated_asm, InlineAsmArch::AArch64, None).unwrap();
writeln!(generated_asm, ", [x19, 0x{:x}]", offset.bytes()).unwrap();
}
InlineAsmArch::RiscV64 => {
generated_asm.push_str(" sd ");
reg.emit(generated_asm, InlineAsmArch::RiscV64, None).unwrap();
writeln!(generated_asm, ", 0x{:x}(s1)", offset.bytes()).unwrap();
}
_ => unimplemented!("save_register for {:?}", arch),
}
}
@ -815,6 +861,11 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> {
reg.emit(generated_asm, InlineAsmArch::AArch64, None).unwrap();
writeln!(generated_asm, ", [x19, 0x{:x}]", offset.bytes()).unwrap();
}
InlineAsmArch::RiscV64 => {
generated_asm.push_str(" ld ");
reg.emit(generated_asm, InlineAsmArch::RiscV64, None).unwrap();
writeln!(generated_asm, ", 0x{:x}(s1)", offset.bytes()).unwrap();
}
_ => unimplemented!("restore_register for {:?}", arch),
}
}

8
compiler/rustc_codegen_cranelift/src/lib.rs
View file

@ -1,6 +1,6 @@
#![cfg_attr(not(bootstrap), allow(internal_features))]
#![cfg_attr(not(bootstrap), feature(rustdoc_internals))]
#![cfg_attr(not(bootstrap), doc(rust_logo))]
#![cfg_attr(all(doc, not(bootstrap)), allow(internal_features))]
#![cfg_attr(all(doc, not(bootstrap)), feature(rustdoc_internals))]
#![cfg_attr(all(doc, not(bootstrap)), doc(rust_logo))]
#![feature(rustc_private)]
// Note: please avoid adding other feature gates where possible
#![warn(rust_2018_idioms)]
@ -189,7 +189,7 @@ impl CodegenBackend for CraneliftCodegenBackend {
}
fn target_features(&self, _sess: &Session, _allow_unstable: bool) -> Vec<rustc_span::Symbol> {
vec![]
vec![] // FIXME necessary for #[cfg(target_feature]
}
fn print_version(&self) {