Recapitalise ARMvX{-Y} to ArmvX{-Y}
Yes it looks weird, but this is how Arm write it now. I left ARM64 alone, because it's a Microsoft/Apple term but not an Arm term (they have Armv8-A and Armv9-A architectures, which say that A64 instructions are executed when in the Aarch64 state), and I don't want to get into that, especially for a Tier 1 target.
This commit is contained in:
Jonathan Pallant
parent
8cea4f3e1e
commit
de0c02c9ab
15 changed files with 81 additions and 81 deletions
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@ -89,9 +89,9 @@ target | notes
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`aarch64-apple-darwin` | ARM64 macOS (11.0+, Big Sur+)
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`aarch64-pc-windows-msvc` | ARM64 Windows MSVC
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`aarch64-unknown-linux-musl` | ARM64 Linux with musl 1.2.3
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`arm-unknown-linux-gnueabi` | ARMv6 Linux (kernel 3.2, glibc 2.17)
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`arm-unknown-linux-gnueabihf` | ARMv6 Linux, hardfloat (kernel 3.2, glibc 2.17)
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`armv7-unknown-linux-gnueabihf` | ARMv7-A Linux, hardfloat (kernel 3.2, glibc 2.17)
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`arm-unknown-linux-gnueabi` | Armv6 Linux (kernel 3.2, glibc 2.17)
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`arm-unknown-linux-gnueabihf` | Armv6 Linux, hardfloat (kernel 3.2, glibc 2.17)
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`armv7-unknown-linux-gnueabihf` | Armv7-A Linux, hardfloat (kernel 3.2, glibc 2.17)
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[`loongarch64-unknown-linux-gnu`](platform-support/loongarch-linux.md) | LoongArch64 Linux, LP64D ABI (kernel 5.19, glibc 2.36)
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`powerpc-unknown-linux-gnu` | PowerPC Linux (kernel 3.2, glibc 2.17)
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`powerpc64-unknown-linux-gnu` | PPC64 Linux (kernel 3.2, glibc 2.17)
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@ -143,21 +143,21 @@ target | std | notes
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`aarch64-unknown-none-softfloat` | * | Bare ARM64, softfloat
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`aarch64-unknown-none` | * | Bare ARM64, hardfloat
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[`aarch64-unknown-uefi`](platform-support/unknown-uefi.md) | ? | ARM64 UEFI
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[`arm-linux-androideabi`](platform-support/android.md) | ✓ | ARMv6 Android
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`arm-unknown-linux-musleabi` | ✓ | ARMv6 Linux with musl 1.2.3
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`arm-unknown-linux-musleabihf` | ✓ | ARMv6 Linux with musl 1.2.3, hardfloat
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[`armebv7r-none-eabi`](platform-support/armv7r-none-eabi.md) | * | Bare ARMv7-R, Big Endian
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[`armebv7r-none-eabihf`](platform-support/armv7r-none-eabi.md) | * | Bare ARMv7-R, Big Endian, hardfloat
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`armv5te-unknown-linux-gnueabi` | ✓ | ARMv5TE Linux (kernel 4.4, glibc 2.23)
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`armv5te-unknown-linux-musleabi` | ✓ | ARMv5TE Linux with musl 1.2.3
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[`armv7-linux-androideabi`](platform-support/android.md) | ✓ | ARMv7-A Android
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`armv7-unknown-linux-gnueabi` | ✓ | ARMv7-A Linux (kernel 4.15, glibc 2.27)
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`armv7-unknown-linux-musleabi` | ✓ | ARMv7-A Linux with musl 1.2.3
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`armv7-unknown-linux-musleabihf` | ✓ | ARMv7-A Linux with musl 1.2.3, hardfloat
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[`armv7-unknown-linux-ohos`](platform-support/openharmony.md) | ✓ | ARMv7-A OpenHarmony
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[`armv7a-none-eabi`](platform-support/arm-none-eabi.md) | * | Bare ARMv7-A
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[`armv7r-none-eabi`](platform-support/armv7r-none-eabi.md) | * | Bare ARMv7-R
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[`armv7r-none-eabihf`](platform-support/armv7r-none-eabi.md) | * | Bare ARMv7-R, hardfloat
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[`arm-linux-androideabi`](platform-support/android.md) | ✓ | Armv6 Android
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`arm-unknown-linux-musleabi` | ✓ | Armv6 Linux with musl 1.2.3
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`arm-unknown-linux-musleabihf` | ✓ | Armv6 Linux with musl 1.2.3, hardfloat
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[`armebv7r-none-eabi`](platform-support/armv7r-none-eabi.md) | * | Bare Armv7-R, Big Endian
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[`armebv7r-none-eabihf`](platform-support/armv7r-none-eabi.md) | * | Bare Armv7-R, Big Endian, hardfloat
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`armv5te-unknown-linux-gnueabi` | ✓ | Armv5TE Linux (kernel 4.4, glibc 2.23)
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`armv5te-unknown-linux-musleabi` | ✓ | Armv5TE Linux with musl 1.2.3
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[`armv7-linux-androideabi`](platform-support/android.md) | ✓ | Armv7-A Android
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`armv7-unknown-linux-gnueabi` | ✓ | Armv7-A Linux (kernel 4.15, glibc 2.27)
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`armv7-unknown-linux-musleabi` | ✓ | Armv7-A Linux with musl 1.2.3
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`armv7-unknown-linux-musleabihf` | ✓ | Armv7-A Linux with musl 1.2.3, hardfloat
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[`armv7-unknown-linux-ohos`](platform-support/openharmony.md) | ✓ | Armv7-A OpenHarmony
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[`armv7a-none-eabi`](platform-support/arm-none-eabi.md) | * | Bare Armv7-A
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[`armv7r-none-eabi`](platform-support/armv7r-none-eabi.md) | * | Bare Armv7-R
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[`armv7r-none-eabihf`](platform-support/armv7r-none-eabi.md) | * | Bare Armv7-R, hardfloat
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`i586-pc-windows-msvc` | * | 32-bit Windows w/o SSE [^x86_32-floats-x87]
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`i586-unknown-linux-gnu` | ✓ | 32-bit Linux w/o SSE (kernel 3.2, glibc 2.17) [^x86_32-floats-x87]
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`i586-unknown-linux-musl` | ✓ | 32-bit Linux w/o SSE, musl 1.2.3 [^x86_32-floats-x87]
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@ -178,15 +178,15 @@ target | std | notes
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`riscv64imac-unknown-none-elf` | * | Bare RISC-V (RV64IMAC ISA)
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`sparc64-unknown-linux-gnu` | ✓ | SPARC Linux (kernel 4.4, glibc 2.23)
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`sparcv9-sun-solaris` | ✓ | SPARC Solaris 11, illumos
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[`thumbv6m-none-eabi`](platform-support/thumbv6m-none-eabi.md) | * | Bare ARMv6-M
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[`thumbv7em-none-eabi`](platform-support/thumbv7em-none-eabi.md) | * | Bare ARMv7E-M
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[`thumbv7em-none-eabihf`](platform-support/thumbv7em-none-eabi.md) | * | Bare ARMV7E-M, hardfloat
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[`thumbv7m-none-eabi`](platform-support/thumbv7m-none-eabi.md) | * | Bare ARMv7-M
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[`thumbv7neon-linux-androideabi`](platform-support/android.md) | ✓ | Thumb2-mode ARMv7-A Android with NEON
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`thumbv7neon-unknown-linux-gnueabihf` | ✓ | Thumb2-mode ARMv7-A Linux with NEON (kernel 4.4, glibc 2.23)
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[`thumbv8m.base-none-eabi`](platform-support/thumbv8m.base-none-eabi.md) | * | Bare ARMv8-M Baseline
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[`thumbv8m.main-none-eabi`](platform-support/thumbv8m.main-none-eabi.md) | * | Bare ARMv8-M Mainline
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[`thumbv8m.main-none-eabihf`](platform-support/thumbv8m.main-none-eabi.md) | * | Bare ARMv8-M Mainline, hardfloat
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[`thumbv6m-none-eabi`](platform-support/thumbv6m-none-eabi.md) | * | Bare Armv6-M
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[`thumbv7em-none-eabi`](platform-support/thumbv7em-none-eabi.md) | * | Bare Armv7E-M
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[`thumbv7em-none-eabihf`](platform-support/thumbv7em-none-eabi.md) | * | Bare Armv7E-M, hardfloat
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[`thumbv7m-none-eabi`](platform-support/thumbv7m-none-eabi.md) | * | Bare Armv7-M
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[`thumbv7neon-linux-androideabi`](platform-support/android.md) | ✓ | Thumb2-mode Armv7-A Android with NEON
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`thumbv7neon-unknown-linux-gnueabihf` | ✓ | Thumb2-mode Armv7-A Linux with NEON (kernel 4.4, glibc 2.23)
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[`thumbv8m.base-none-eabi`](platform-support/thumbv8m.base-none-eabi.md) | * | Bare Armv8-M Baseline
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[`thumbv8m.main-none-eabi`](platform-support/thumbv8m.main-none-eabi.md) | * | Bare Armv8-M Mainline
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[`thumbv8m.main-none-eabihf`](platform-support/thumbv8m.main-none-eabi.md) | * | Bare Armv8-M Mainline, hardfloat
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`wasm32-unknown-emscripten` | ✓ | WebAssembly via Emscripten
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`wasm32-unknown-unknown` | ✓ | WebAssembly
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`wasm32-wasi` | ✓ | WebAssembly with WASI (undergoing a [rename to `wasm32-wasip1`][wasi-rename])
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@ -264,27 +264,27 @@ target | std | host | notes
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`aarch64_be-unknown-linux-gnu_ilp32` | ✓ | ✓ | ARM64 Linux (big-endian, ILP32 ABI)
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`aarch64_be-unknown-linux-gnu` | ✓ | ✓ | ARM64 Linux (big-endian)
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[`aarch64_be-unknown-netbsd`](platform-support/netbsd.md) | ✓ | ✓ | ARM64 NetBSD (big-endian)
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[`arm64_32-apple-watchos`](platform-support/apple-watchos.md) | ✓ | | ARM Apple WatchOS 64-bit with 32-bit pointers
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[`armeb-unknown-linux-gnueabi`](platform-support/armeb-unknown-linux-gnueabi.md) | ✓ | ? | ARM BE8 the default ARM big-endian architecture since [ARMv6](https://developer.arm.com/documentation/101754/0616/armlink-Reference/armlink-Command-line-Options/--be8?lang=en).
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[`armv4t-none-eabi`](platform-support/armv4t-none-eabi.md) | * | | Bare ARMv4T
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`armv4t-unknown-linux-gnueabi` | ? | | ARMv4T Linux
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[`armv5te-none-eabi`](platform-support/armv5te-none-eabi.md) | * | | Bare ARMv5TE
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`armv5te-unknown-linux-uclibceabi` | ? | | ARMv5TE Linux with uClibc
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`armv6-unknown-freebsd` | ✓ | ✓ | ARMv6 FreeBSD
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[`armv6-unknown-netbsd-eabihf`](platform-support/netbsd.md) | ✓ | ✓ | ARMv6 NetBSD w/hard-float
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[`armv6k-nintendo-3ds`](platform-support/armv6k-nintendo-3ds.md) | ? | | ARMv6K Nintendo 3DS, Horizon (Requires devkitARM toolchain)
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[`armv7-sony-vita-newlibeabihf`](platform-support/armv7-sony-vita-newlibeabihf.md) | ✓ | | ARMv7-A Cortex-A9 Sony PlayStation Vita (requires VITASDK toolchain)
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[`armv7-unknown-linux-uclibceabi`](platform-support/armv7-unknown-linux-uclibceabi.md) | ✓ | ✓ | ARMv7-A Linux with uClibc, softfloat
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[`armv7-unknown-linux-uclibceabihf`](platform-support/armv7-unknown-linux-uclibceabihf.md) | ✓ | ? | ARMv7-A Linux with uClibc, hardfloat
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`armv7-unknown-freebsd` | ✓ | ✓ | ARMv7-A FreeBSD
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[`armv7-unknown-netbsd-eabihf`](platform-support/netbsd.md) | ✓ | ✓ | ARMv7-A NetBSD w/hard-float
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`armv7-wrs-vxworks-eabihf` | ? | | ARMv7-A for VxWorks
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[`arm64_32-apple-watchos`](platform-support/apple-watchos.md) | ✓ | | Arm Apple WatchOS 64-bit with 32-bit pointers
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[`armeb-unknown-linux-gnueabi`](platform-support/armeb-unknown-linux-gnueabi.md) | ✓ | ? | Arm BE8 the default Arm big-endian architecture since [Armv6](https://developer.arm.com/documentation/101754/0616/armlink-Reference/armlink-Command-line-Options/--be8?lang=en).
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[`armv4t-none-eabi`](platform-support/armv4t-none-eabi.md) | * | | Bare Armv4T
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`armv4t-unknown-linux-gnueabi` | ? | | Armv4T Linux
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[`armv5te-none-eabi`](platform-support/armv5te-none-eabi.md) | * | | Bare Armv5TE
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`armv5te-unknown-linux-uclibceabi` | ? | | Armv5TE Linux with uClibc
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`armv6-unknown-freebsd` | ✓ | ✓ | Armv6 FreeBSD
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[`armv6-unknown-netbsd-eabihf`](platform-support/netbsd.md) | ✓ | ✓ | Armv6 NetBSD w/hard-float
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[`armv6k-nintendo-3ds`](platform-support/armv6k-nintendo-3ds.md) | ? | | Armv6k Nintendo 3DS, Horizon (Requires devkitARM toolchain)
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[`armv7-sony-vita-newlibeabihf`](platform-support/armv7-sony-vita-newlibeabihf.md) | ✓ | | Armv7-A Cortex-A9 Sony PlayStation Vita (requires VITASDK toolchain)
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[`armv7-unknown-linux-uclibceabi`](platform-support/armv7-unknown-linux-uclibceabi.md) | ✓ | ✓ | Armv7-A Linux with uClibc, softfloat
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[`armv7-unknown-linux-uclibceabihf`](platform-support/armv7-unknown-linux-uclibceabihf.md) | ✓ | ? | Armv7-A Linux with uClibc, hardfloat
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`armv7-unknown-freebsd` | ✓ | ✓ | Armv7-A FreeBSD
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[`armv7-unknown-netbsd-eabihf`](platform-support/netbsd.md) | ✓ | ✓ | Armv7-A NetBSD w/hard-float
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`armv7-wrs-vxworks-eabihf` | ? | | Armv7-A for VxWorks
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[`armv7a-kmc-solid_asp3-eabi`](platform-support/kmc-solid.md) | ✓ | | ARM SOLID with TOPPERS/ASP3
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[`armv7a-kmc-solid_asp3-eabihf`](platform-support/kmc-solid.md) | ✓ | | ARM SOLID with TOPPERS/ASP3, hardfloat
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[`armv7a-none-eabihf`](platform-support/arm-none-eabi.md) | * | | Bare ARMv7-A, hardfloat
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[`armv7k-apple-watchos`](platform-support/apple-watchos.md) | ✓ | | ARMv7-A Apple WatchOS
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`armv7s-apple-ios` | ✓ | | ARMv7-A Apple-A6 Apple iOS
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[`armv8r-none-eabihf`](platform-support/armv8r-none-eabihf.md) | * | | Bare ARMv8-R, hardfloat
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[`armv7a-none-eabihf`](platform-support/arm-none-eabi.md) | * | | Bare Armv7-A, hardfloat
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[`armv7k-apple-watchos`](platform-support/apple-watchos.md) | ✓ | | Armv7-A Apple WatchOS
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`armv7s-apple-ios` | ✓ | | Armv7-A Apple-A6 Apple iOS
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[`armv8r-none-eabihf`](platform-support/armv8r-none-eabihf.md) | * | | Bare Armv8-R, hardfloat
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`avr-unknown-gnu-atmega328` | * | | AVR. Requires `-Z build-std=core`
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`bpfeb-unknown-none` | * | | BPF (big endian)
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`bpfel-unknown-none` | * | | BPF (little endian)
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@ -360,11 +360,11 @@ target | std | host | notes
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[`sparc-unknown-none-elf`](./platform-support/sparc-unknown-none-elf.md) | * | | Bare 32-bit SPARC V7+
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[`sparc64-unknown-netbsd`](platform-support/netbsd.md) | ✓ | ✓ | NetBSD/sparc64
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[`sparc64-unknown-openbsd`](platform-support/openbsd.md) | ✓ | ✓ | OpenBSD/sparc64
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[`thumbv4t-none-eabi`](platform-support/armv4t-none-eabi.md) | * | | Thumb-mode Bare ARMv4T
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[`thumbv5te-none-eabi`](platform-support/armv5te-none-eabi.md) | * | | Thumb-mode Bare ARMv5TE
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[`thumbv4t-none-eabi`](platform-support/armv4t-none-eabi.md) | * | | Thumb-mode Bare Armv4T
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[`thumbv5te-none-eabi`](platform-support/armv5te-none-eabi.md) | * | | Thumb-mode Bare Armv5TE
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`thumbv7a-pc-windows-msvc` | ? | |
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`thumbv7a-uwp-windows-msvc` | ✓ | |
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`thumbv7neon-unknown-linux-musleabihf` | ? | | Thumb2-mode ARMv7-A Linux with NEON, musl 1.2.3
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`thumbv7neon-unknown-linux-musleabihf` | ? | | Thumb2-mode Armv7-A Linux with NEON, musl 1.2.3
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[`wasm32-wasip2`](platform-support/wasm32-wasip2.md) | ✓ | | WebAssembly
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[`wasm64-unknown-unknown`](platform-support/wasm64-unknown-unknown.md) | ? | | WebAssembly
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`x86_64-apple-ios-macabi` | ✓ | | Apple Catalyst on x86_64
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## Common Target Details
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This documentation covers details that apply to a range of bare-metal targets
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for 32-bit ARM CPUs. In addition, target specific details may be covered in
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for 32-bit Arm CPUs. In addition, target specific details may be covered in
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their own document.
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If a target ends in `eabi`, that target uses the so-called *soft-float ABI*:
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@ -1,22 +1,22 @@
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# armeb-unknown-linux-gnueabi
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**Tier: 3**
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Target for cross-compiling Linux user-mode applications targeting the ARM BE8 architecture.
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Target for cross-compiling Linux user-mode applications targeting the Arm BE8 architecture.
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## Overview
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BE8 architecture retains the same little-endian ordered code-stream used by conventional little endian ARM systems, however the data accesses are in big-endian. BE8 is used primarily in high-performance networking applications where the ability to read packets in their native "Network Byte Order" is important (many network protocols transmit data in big-endian byte order for their wire formats).
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BE8 architecture retains the same little-endian ordered code-stream used by conventional little endian Arm systems, however the data accesses are in big-endian. BE8 is used primarily in high-performance networking applications where the ability to read packets in their native "Network Byte Order" is important (many network protocols transmit data in big-endian byte order for their wire formats).
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## History
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BE8 architecture is the default big-endian architecture for ARM since [ARMv6](https://developer.arm.com/documentation/101754/0616/armlink-Reference/armlink-Command-line-Options/--be8?lang=en). It's predecessor, used for ARMv4 and ARMv5 devices was [BE32](https://developer.arm.com/documentation/dui0474/j/linker-command-line-options/--be32). On ARMv6 architecture, endianness can be configured via [system registers](https://developer.arm.com/documentation/ddi0290/g/unaligned-and-mixed-endian-data-access-support/mixed-endian-access-support/interaction-between-the-bus-protocol-and-the-core-endianness). However, BE32 was withdrawn for [ARMv7](https://developer.arm.com/documentation/ddi0406/cb/Appendixes/Deprecated-and-Obsolete-Features/Obsolete-features/Support-for-BE-32-endianness-model) onwards.
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BE8 architecture is the default big-endian architecture for Arm since [Armv6](https://developer.arm.com/documentation/101754/0616/armlink-Reference/armlink-Command-line-Options/--be8?lang=en). It's predecessor, used for Armv4 and Armv5 devices was [BE32](https://developer.arm.com/documentation/dui0474/j/linker-command-line-options/--be32). On Armv6 architecture, endianness can be configured via [system registers](https://developer.arm.com/documentation/ddi0290/g/unaligned-and-mixed-endian-data-access-support/mixed-endian-access-support/interaction-between-the-bus-protocol-and-the-core-endianness). However, BE32 was withdrawn for [Armv7](https://developer.arm.com/documentation/ddi0406/cb/Appendixes/Deprecated-and-Obsolete-Features/Obsolete-features/Support-for-BE-32-endianness-model) onwards.
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## Target Maintainers
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* [@WorksButNotTested](https://github.com/WorksButNotTested)
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## Requirements
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The target is cross-compiled. This target supports `std` in the normal way (indeed only nominal changes are required from the standard ARM configuration).
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The target is cross-compiled. This target supports `std` in the normal way (indeed only nominal changes are required from the standard Arm configuration).
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## Target definition
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The target definition can be seen [here](https://github.com/rust-lang/rust/tree/master/compiler/rustc_target/src/spec/armeb_unknown_linux_gnueabi.rs). In particular, it should be noted that the `features` specify that this target is built for the ARMv8 core. Though this can likely be modified as required.
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The target definition can be seen [here](https://github.com/rust-lang/rust/tree/master/compiler/rustc_target/src/spec/armeb_unknown_linux_gnueabi.rs). In particular, it should be noted that the `features` specify that this target is built for the Armv8 core. Though this can likely be modified as required.
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## Building the target
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Because it is Tier 3, rust does not yet ship pre-compiled artifacts for this target.
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@ -2,12 +2,12 @@
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Tier 3
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Bare-metal target for any cpu in the ARMv4T architecture family, supporting
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ARM/Thumb code interworking (aka `a32`/`t32`), with ARM code as the default code
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Bare-metal target for any cpu in the Armv4T architecture family, supporting
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ARM/Thumb code interworking (aka `A32`/`T32`), with ARM code as the default code
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generation.
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In particular this supports the Game Boy Advance (GBA), but there's nothing
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GBA-specific with this target, so any ARMv4T device should work fine.
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GBA-specific with this target, so any Armv4T device should work fine.
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See [`arm-none-eabi`](arm-none-eabi.md) for information applicable to all
|
||||
`arm-none-eabi` targets.
|
||||
|
|
|
|||
|
|
@ -2,11 +2,11 @@
|
|||
|
||||
**Tier: 3**
|
||||
|
||||
Bare-metal target for any cpu in the ARMv5TE architecture family, supporting
|
||||
ARM/Thumb code interworking (aka `a32`/`t32`), with `a32` code as the default code
|
||||
Bare-metal target for any cpu in the Armv5TE architecture family, supporting
|
||||
ARM/Thumb code interworking (aka `A32`/`T32`), with `A32` code as the default code
|
||||
generation.
|
||||
|
||||
The `thumbv5te-none-eabi` target is the same as this one, but the instruction set defaults to `t32`.
|
||||
The `thumbv5te-none-eabi` target is the same as this one, but the instruction set defaults to `T32`.
|
||||
|
||||
See [`arm-none-eabi`](arm-none-eabi.md) for information applicable to all
|
||||
`arm-none-eabi` targets.
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
|
||||
**Tier: 3**
|
||||
|
||||
The Nintendo 3DS platform, which has an ARMv6K processor, and its associated
|
||||
The Nintendo 3DS platform, which has an Armv6k processor, and its associated
|
||||
operating system (`horizon`).
|
||||
|
||||
Rust support for this target is not affiliated with Nintendo, and is not derived
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
|
||||
**Tier: 3**
|
||||
|
||||
This target supports ARMv7 softfloat CPUs and uses the uclibc-ng standard library. This is a common configuration on many consumer routers (e.g., Netgear R7000, Asus RT-AC68U).
|
||||
This target supports Armv7-A softfloat CPUs and uses the uclibc-ng standard library. This is a common configuration on many consumer routers (e.g., Netgear R7000, Asus RT-AC68U).
|
||||
|
||||
## Target maintainers
|
||||
|
||||
|
|
@ -16,7 +16,7 @@ This target supports host tools and std.
|
|||
|
||||
## Building the target
|
||||
|
||||
You will need to download or build a `'C'` cross toolchain that targets ARMv7 softfloat and that uses the uclibc-ng standard library. If your target hardware is something like a router or an embedded device, keep in mind that manufacturer supplied SDKs for this class of CPU could be outdated and potentially unsuitable for bootstrapping rust.
|
||||
You will need to download or build a `'C'` cross toolchain that targets Armv7-A softfloat and that uses the uclibc-ng standard library. If your target hardware is something like a router or an embedded device, keep in mind that manufacturer supplied SDKs for this class of CPU could be outdated and potentially unsuitable for bootstrapping rust.
|
||||
|
||||
[Here](https://github.com/lancethepants/tomatoware-toolchain) is a sample toolchain that is built using [buildroot](https://buildroot.org/). It uses modern toolchain components, older thus universal kernel headers (2.6.36.4), and is used for a project called [Tomatoware](https://github.com/lancethepants/tomatoware). This toolchain is patched so that its sysroot is located at /mmc (e.g., /mmc/bin, /mmc/lib, /mmc/include). This is useful in scenarios where the root filesystem is read-only but you are able attach external storage loaded with user applications. Tomatoware is an example of this that even allows you to run various compilers and developer tools natively on the target device.
|
||||
|
||||
|
|
@ -46,7 +46,7 @@ The following assumes you are using the Tomatoware toolchain and environment. Ad
|
|||
|
||||
### Native compilation
|
||||
|
||||
Since this target supports host tools, you can natively build rust applications directly on your target device. This can be convenient because it removes the complexities of cross compiling and you can immediately test and deploy your binaries. One downside is that compiling on your ARMv7 CPU will probably be much slower than cross compilation on your x86 machine.
|
||||
Since this target supports host tools, you can natively build rust applications directly on your target device. This can be convenient because it removes the complexities of cross compiling and you can immediately test and deploy your binaries. One downside is that compiling on your Armv7-A CPU will probably be much slower than cross compilation on your x86 machine.
|
||||
|
||||
To setup native compilation:
|
||||
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
|
||||
**Tier: 3**
|
||||
|
||||
This tier supports the ARMv7 processor running a Linux kernel and uClibc-ng standard library. It provides full support for rust and the rust standard library.
|
||||
This tier supports the Armv7-A processor running a Linux kernel and uClibc-ng standard library. It provides full support for rust and the rust standard library.
|
||||
|
||||
## Designated Developers
|
||||
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
|
||||
**Tier: 2**
|
||||
|
||||
Bare-metal target for CPUs in the ARMv7-R architecture family, supporting
|
||||
Bare-metal target for CPUs in the Armv7-R architecture family, supporting
|
||||
dual ARM/Thumb mode, with ARM mode as the default.
|
||||
|
||||
Processors in this family include the [Arm Cortex-R4, 5, 7, and 8][cortex-r].
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
|
||||
**Tier: 3**
|
||||
|
||||
Bare-metal target for CPUs in the ARMv8-R architecture family, supporting
|
||||
Bare-metal target for CPUs in the Armv8-R architecture family, supporting
|
||||
dual ARM/Thumb mode, with ARM mode as the default.
|
||||
|
||||
Processors in this family include the Arm [Cortex-R52][cortex-r52]
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
|
||||
**Tier: 2**
|
||||
|
||||
Bare-metal target for CPUs in the [ARMv6-M] architecture family, supporting a
|
||||
Bare-metal target for CPUs in the [Armv6-M] architecture family, supporting a
|
||||
subset of the [T32 ISA][t32-isa].
|
||||
|
||||
Processors in this family include the:
|
||||
|
|
@ -16,10 +16,10 @@ See [`arm-none-eabi`](arm-none-eabi.md) for information applicable to all
|
|||
|
||||
This target uses the soft-float ABI: functions which take `f32` or `f64` as
|
||||
arguments will have those values packed into integer registers. This is the
|
||||
only option because there is no FPU support in [ARMv6-M].
|
||||
only option because there is no FPU support in [Armv6-M].
|
||||
|
||||
[t32-isa]: https://developer.arm.com/Architectures/T32%20Instruction%20Set%20Architecture
|
||||
[ARMv6-M]: https://developer.arm.com/documentation/ddi0419/latest/
|
||||
[Armv6-M]: https://developer.arm.com/documentation/ddi0419/latest/
|
||||
[cortex-m0]: https://developer.arm.com/Processors/Cortex-M0
|
||||
[cortex-m0plus]: https://developer.arm.com/Processors/Cortex-M0+
|
||||
[cortex-m1]: https://developer.arm.com/Processors/Cortex-M1
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
|
||||
**Tier: 2**
|
||||
|
||||
Bare-metal target for CPUs in the [ARMv7E-M] architecture family, supporting a
|
||||
Bare-metal target for CPUs in the [Armv7E-M] architecture family, supporting a
|
||||
subset of the [T32 ISA][t32-isa].
|
||||
|
||||
Processors in this family include the:
|
||||
|
|
@ -15,7 +15,7 @@ See [`arm-none-eabi`](arm-none-eabi.md) for information applicable to all
|
|||
`eabihf` ABI.
|
||||
|
||||
[t32-isa]: https://developer.arm.com/Architectures/T32%20Instruction%20Set%20Architecture
|
||||
[ARMv7E-M]: https://developer.arm.com/documentation/ddi0403/latest/
|
||||
[Armv7E-M]: https://developer.arm.com/documentation/ddi0403/latest/
|
||||
[cortex-m4]: https://developer.arm.com/Processors/Cortex-M4
|
||||
[cortex-m7]: https://developer.arm.com/Processors/Cortex-M7
|
||||
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
|
||||
**Tier: 2**
|
||||
|
||||
Bare-metal target for CPUs in the [ARMv7-M] architecture family, supporting a
|
||||
Bare-metal target for CPUs in the [Armv7-M] architecture family, supporting a
|
||||
subset of the [T32 ISA][t32-isa].
|
||||
|
||||
Processors in this family include the:
|
||||
|
|
@ -14,10 +14,10 @@ See [`arm-none-eabi`](arm-none-eabi.md) for information applicable to all
|
|||
|
||||
This target uses the soft-float ABI: functions which take `f32` or `f64` as
|
||||
arguments will have those values packed into integer registers. This is the
|
||||
only option because there is no FPU support in [ARMv7-M].
|
||||
only option because there is no FPU support in [Armv7-M].
|
||||
|
||||
[t32-isa]: https://developer.arm.com/Architectures/T32%20Instruction%20Set%20Architecture
|
||||
[ARMv7-M]: https://developer.arm.com/documentation/ddi0403/latest/
|
||||
[Armv7-M]: https://developer.arm.com/documentation/ddi0403/latest/
|
||||
[cortex-m3]: https://developer.arm.com/Processors/Cortex-M3
|
||||
|
||||
## Target maintainers
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
|
||||
**Tier: 2**
|
||||
|
||||
Bare-metal target for CPUs in the Baseline [ARMv8-M] architecture family,
|
||||
Bare-metal target for CPUs in the Baseline [Armv8-M] architecture family,
|
||||
supporting a subset of the [T32 ISA][t32-isa].
|
||||
|
||||
Processors in this family include the:
|
||||
|
|
@ -14,10 +14,10 @@ See [`arm-none-eabi`](arm-none-eabi.md) for information applicable to all
|
|||
|
||||
This target uses the soft-float ABI: functions which take `f32` or `f64` as
|
||||
arguments will have those values packed into integer registers. This is the
|
||||
only option because there is no FPU support in [ARMv8-M] Baseline.
|
||||
only option because there is no FPU support in [Armv8-M] Baseline.
|
||||
|
||||
[t32-isa]: https://developer.arm.com/Architectures/T32%20Instruction%20Set%20Architecture
|
||||
[ARMv8-M]: https://developer.arm.com/documentation/ddi0553/latest/
|
||||
[Armv8-M]: https://developer.arm.com/documentation/ddi0553/latest/
|
||||
[cortex-m23]: https://developer.arm.com/Processors/Cortex-M23
|
||||
|
||||
## Target maintainers
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
|
||||
**Tier: 2**
|
||||
|
||||
Bare-metal target for CPUs in the Mainline [ARMv8-M] architecture family,
|
||||
Bare-metal target for CPUs in the Mainline [Armv8-M] architecture family,
|
||||
supporting a subset of the [T32 ISA][t32-isa].
|
||||
|
||||
Processors in this family include the:
|
||||
|
|
@ -17,7 +17,7 @@ See [`arm-none-eabi`](arm-none-eabi.md) for information applicable to all
|
|||
`eabihf` ABI.
|
||||
|
||||
[t32-isa]: https://developer.arm.com/Architectures/T32%20Instruction%20Set%20Architecture
|
||||
[ARMv8-M]: https://developer.arm.com/documentation/ddi0553/latest/
|
||||
[Armv8-M]: https://developer.arm.com/documentation/ddi0553/latest/
|
||||
[cortex-m33]: https://developer.arm.com/Processors/Cortex-M33
|
||||
[cortex-m35p]: https://developer.arm.com/Processors/Cortex-M35P
|
||||
[cortex-m55]: https://developer.arm.com/Processors/Cortex-M55
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue