Mark scalar layout unions so that backends that do not support partially initialized scalars can special case them.
This commit is contained in:
Oli Scherer
parent
2ed6786404
commit
d32ce37a17
37 changed files with 356 additions and 288 deletions
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@ -753,7 +753,7 @@ fn dummy_output_type<'ll>(cx: &CodegenCx<'ll, '_>, reg: InlineAsmRegClass) -> &'
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/// Helper function to get the LLVM type for a Scalar. Pointers are returned as
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/// the equivalent integer type.
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fn llvm_asm_scalar_type<'ll>(cx: &CodegenCx<'ll, '_>, scalar: Scalar) -> &'ll Type {
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match scalar.value {
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match scalar.primitive() {
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Primitive::Int(Integer::I8, _) => cx.type_i8(),
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Primitive::Int(Integer::I16, _) => cx.type_i16(),
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Primitive::Int(Integer::I32, _) => cx.type_i32(),
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@ -774,7 +774,7 @@ fn llvm_fixup_input<'ll, 'tcx>(
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) -> &'ll Value {
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match (reg, layout.abi) {
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(InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg), Abi::Scalar(s)) => {
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if let Primitive::Int(Integer::I8, _) = s.value {
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if let Primitive::Int(Integer::I8, _) = s.primitive() {
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let vec_ty = bx.cx.type_vector(bx.cx.type_i8(), 8);
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bx.insert_element(bx.const_undef(vec_ty), value, bx.const_i32(0))
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} else {
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@ -785,7 +785,7 @@ fn llvm_fixup_input<'ll, 'tcx>(
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let elem_ty = llvm_asm_scalar_type(bx.cx, s);
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let count = 16 / layout.size.bytes();
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let vec_ty = bx.cx.type_vector(elem_ty, count);
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if let Primitive::Pointer = s.value {
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if let Primitive::Pointer = s.primitive() {
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value = bx.ptrtoint(value, bx.cx.type_isize());
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}
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bx.insert_element(bx.const_undef(vec_ty), value, bx.const_i32(0))
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@ -800,7 +800,7 @@ fn llvm_fixup_input<'ll, 'tcx>(
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bx.shuffle_vector(value, bx.const_undef(vec_ty), bx.const_vector(&indices))
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}
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(InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_abcd), Abi::Scalar(s))
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if s.value == Primitive::F64 =>
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if s.primitive() == Primitive::F64 =>
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{
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bx.bitcast(value, bx.cx.type_i64())
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}
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@ -812,7 +812,7 @@ fn llvm_fixup_input<'ll, 'tcx>(
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InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg | ArmInlineAsmRegClass::sreg_low16),
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Abi::Scalar(s),
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) => {
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if let Primitive::Int(Integer::I32, _) = s.value {
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if let Primitive::Int(Integer::I32, _) = s.primitive() {
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bx.bitcast(value, bx.cx.type_f32())
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} else {
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value
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@ -826,19 +826,21 @@ fn llvm_fixup_input<'ll, 'tcx>(
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),
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Abi::Scalar(s),
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) => {
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if let Primitive::Int(Integer::I64, _) = s.value {
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if let Primitive::Int(Integer::I64, _) = s.primitive() {
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bx.bitcast(value, bx.cx.type_f64())
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} else {
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value
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}
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}
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(InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg), Abi::Scalar(s)) => match s.value {
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// MIPS only supports register-length arithmetics.
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Primitive::Int(Integer::I8 | Integer::I16, _) => bx.zext(value, bx.cx.type_i32()),
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Primitive::F32 => bx.bitcast(value, bx.cx.type_i32()),
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Primitive::F64 => bx.bitcast(value, bx.cx.type_i64()),
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_ => value,
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},
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(InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg), Abi::Scalar(s)) => {
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match s.primitive() {
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// MIPS only supports register-length arithmetics.
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Primitive::Int(Integer::I8 | Integer::I16, _) => bx.zext(value, bx.cx.type_i32()),
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Primitive::F32 => bx.bitcast(value, bx.cx.type_i32()),
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Primitive::F64 => bx.bitcast(value, bx.cx.type_i64()),
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_ => value,
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}
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}
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_ => value,
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}
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}
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@ -852,7 +854,7 @@ fn llvm_fixup_output<'ll, 'tcx>(
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) -> &'ll Value {
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match (reg, layout.abi) {
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(InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg), Abi::Scalar(s)) => {
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if let Primitive::Int(Integer::I8, _) = s.value {
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if let Primitive::Int(Integer::I8, _) = s.primitive() {
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bx.extract_element(value, bx.const_i32(0))
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} else {
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value
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@ -860,7 +862,7 @@ fn llvm_fixup_output<'ll, 'tcx>(
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}
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(InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16), Abi::Scalar(s)) => {
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value = bx.extract_element(value, bx.const_i32(0));
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if let Primitive::Pointer = s.value {
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if let Primitive::Pointer = s.primitive() {
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value = bx.inttoptr(value, layout.llvm_type(bx.cx));
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}
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value
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@ -875,7 +877,7 @@ fn llvm_fixup_output<'ll, 'tcx>(
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bx.shuffle_vector(value, bx.const_undef(vec_ty), bx.const_vector(&indices))
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}
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(InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_abcd), Abi::Scalar(s))
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if s.value == Primitive::F64 =>
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if s.primitive() == Primitive::F64 =>
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{
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bx.bitcast(value, bx.cx.type_f64())
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}
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@ -887,7 +889,7 @@ fn llvm_fixup_output<'ll, 'tcx>(
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InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg | ArmInlineAsmRegClass::sreg_low16),
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Abi::Scalar(s),
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) => {
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if let Primitive::Int(Integer::I32, _) = s.value {
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if let Primitive::Int(Integer::I32, _) = s.primitive() {
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bx.bitcast(value, bx.cx.type_i32())
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} else {
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value
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@ -901,20 +903,22 @@ fn llvm_fixup_output<'ll, 'tcx>(
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),
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Abi::Scalar(s),
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) => {
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if let Primitive::Int(Integer::I64, _) = s.value {
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if let Primitive::Int(Integer::I64, _) = s.primitive() {
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bx.bitcast(value, bx.cx.type_i64())
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} else {
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value
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}
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}
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(InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg), Abi::Scalar(s)) => match s.value {
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// MIPS only supports register-length arithmetics.
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Primitive::Int(Integer::I8, _) => bx.trunc(value, bx.cx.type_i8()),
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Primitive::Int(Integer::I16, _) => bx.trunc(value, bx.cx.type_i16()),
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Primitive::F32 => bx.bitcast(value, bx.cx.type_f32()),
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Primitive::F64 => bx.bitcast(value, bx.cx.type_f64()),
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_ => value,
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},
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(InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg), Abi::Scalar(s)) => {
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match s.primitive() {
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// MIPS only supports register-length arithmetics.
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Primitive::Int(Integer::I8, _) => bx.trunc(value, bx.cx.type_i8()),
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Primitive::Int(Integer::I16, _) => bx.trunc(value, bx.cx.type_i16()),
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Primitive::F32 => bx.bitcast(value, bx.cx.type_f32()),
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Primitive::F64 => bx.bitcast(value, bx.cx.type_f64()),
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_ => value,
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}
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}
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_ => value,
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}
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}
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@ -927,7 +931,7 @@ fn llvm_fixup_output_type<'ll, 'tcx>(
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) -> &'ll Type {
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match (reg, layout.abi) {
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(InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg), Abi::Scalar(s)) => {
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if let Primitive::Int(Integer::I8, _) = s.value {
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if let Primitive::Int(Integer::I8, _) = s.primitive() {
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cx.type_vector(cx.type_i8(), 8)
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} else {
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layout.llvm_type(cx)
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@ -946,7 +950,7 @@ fn llvm_fixup_output_type<'ll, 'tcx>(
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cx.type_vector(elem_ty, count * 2)
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}
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(InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_abcd), Abi::Scalar(s))
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if s.value == Primitive::F64 =>
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if s.primitive() == Primitive::F64 =>
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{
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cx.type_i64()
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}
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@ -958,7 +962,7 @@ fn llvm_fixup_output_type<'ll, 'tcx>(
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InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg | ArmInlineAsmRegClass::sreg_low16),
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Abi::Scalar(s),
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) => {
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if let Primitive::Int(Integer::I32, _) = s.value {
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if let Primitive::Int(Integer::I32, _) = s.primitive() {
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cx.type_f32()
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} else {
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layout.llvm_type(cx)
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@ -972,19 +976,21 @@ fn llvm_fixup_output_type<'ll, 'tcx>(
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),
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Abi::Scalar(s),
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) => {
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if let Primitive::Int(Integer::I64, _) = s.value {
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if let Primitive::Int(Integer::I64, _) = s.primitive() {
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cx.type_f64()
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} else {
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layout.llvm_type(cx)
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}
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}
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(InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg), Abi::Scalar(s)) => match s.value {
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// MIPS only supports register-length arithmetics.
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Primitive::Int(Integer::I8 | Integer::I16, _) => cx.type_i32(),
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Primitive::F32 => cx.type_i32(),
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Primitive::F64 => cx.type_i64(),
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_ => layout.llvm_type(cx),
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},
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(InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg), Abi::Scalar(s)) => {
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match s.primitive() {
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// MIPS only supports register-length arithmetics.
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Primitive::Int(Integer::I8 | Integer::I16, _) => cx.type_i32(),
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Primitive::F32 => cx.type_i32(),
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Primitive::F64 => cx.type_i64(),
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_ => layout.llvm_type(cx),
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}
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}
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_ => layout.llvm_type(cx),
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}
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}
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