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Backport another LLVM commit to rustc_apfloat

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Backports LLVM commit:

    [APFloat] convert SNaN to QNaN in convert() and raise Invalid signal

149f5b573c

SNaN to QNaN conversion also matches what my Intel x86_64 hardware does.
This commit is contained in:
est31 2020-10-03 22:01:22 +02:00
parent 7f5008c829
commit d010809c8c
2 changed files with 26 additions and 26 deletions
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25
compiler/rustc_apfloat/src/ieee.rs
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@ -1511,23 +1511,16 @@ impl<S: Semantics, T: Semantics> FloatConvert<IeeeFloat<T>> for IeeeFloat<S> {
sig::set_bit(&mut r.sig, T::PRECISION - 1);
}
// If we are truncating NaN, it is possible that we shifted out all of the
// set bits in a signalling NaN payload. But NaN must remain NaN, so some
// bit in the significand must be set (otherwise it is Inf).
// This can only happen with sNaN. Set the 1st bit after the quiet bit,
// so that we still have an sNaN.
if r.sig[0] == 0 {
assert!(shift < 0, "Should not lose NaN payload on extend");
assert!(T::PRECISION >= 3, "Unexpectedly narrow significand");
assert!(*loses_info, "Missing payload should have set lost info");
sig::set_bit(&mut r.sig, T::PRECISION - 3);
// Convert of sNaN creates qNaN and raises an exception (invalid op).
// This also guarantees that a sNaN does not become Inf on a truncation
// that loses all payload bits.
if self.is_signaling() {
// Quiet signaling NaN.
sig::set_bit(&mut r.sig, T::QNAN_BIT);
status = Status::INVALID_OP;
} else {
status = Status::OK;
}
// gcc forces the Quiet bit on, which means (float)(double)(float_sNan)
// does not give you back the same bits. This is dubious, and we
// don't currently do it. You're really supposed to get
// an invalid operation signal at runtime, but nobody does that.
status = Status::OK;
} else {
*loses_info = false;
status = Status::OK;