Enable loongarch64 LLVM target
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parent
10f7ba562a
commit
ccf5417799
5 changed files with 18 additions and 2 deletions
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@ -10,6 +10,7 @@ const OPTIONAL_COMPONENTS: &[&str] = &[
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"aarch64",
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"aarch64",
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"amdgpu",
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"amdgpu",
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"avr",
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"avr",
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"loongarch",
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"m68k",
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"m68k",
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"mips",
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"mips",
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"powerpc",
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"powerpc",
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@ -146,6 +146,12 @@ extern "C" void LLVMTimeTraceProfilerFinish(const char* FileName) {
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#define SUBTARGET_HEXAGON
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#define SUBTARGET_HEXAGON
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#endif
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#endif
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#ifdef LLVM_COMPONENT_LOONGARCH
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#define SUBTARGET_LOONGARCH SUBTARGET(LoongArch)
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#else
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#define SUBTARGET_LOONGARCH
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#endif
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#define GEN_SUBTARGETS \
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#define GEN_SUBTARGETS \
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SUBTARGET_X86 \
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SUBTARGET_X86 \
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SUBTARGET_ARM \
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SUBTARGET_ARM \
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@ -159,6 +165,7 @@ extern "C" void LLVMTimeTraceProfilerFinish(const char* FileName) {
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SUBTARGET_SPARC \
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SUBTARGET_SPARC \
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SUBTARGET_HEXAGON \
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SUBTARGET_HEXAGON \
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SUBTARGET_RISCV \
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SUBTARGET_RISCV \
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SUBTARGET_LOONGARCH \
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#define SUBTARGET(x) \
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#define SUBTARGET(x) \
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namespace llvm { \
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namespace llvm { \
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@ -102,6 +102,14 @@ pub fn initialize_available_targets() {
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LLVMInitializeM68kAsmPrinter,
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LLVMInitializeM68kAsmPrinter,
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LLVMInitializeM68kAsmParser
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LLVMInitializeM68kAsmParser
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);
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);
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init_target!(
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llvm_component = "loongarch",
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LLVMInitializeLoongArchTargetInfo,
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LLVMInitializeLoongArchTarget,
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LLVMInitializeLoongArchTargetMC,
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LLVMInitializeLoongArchAsmPrinter,
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LLVMInitializeLoongArchAsmParser
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);
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init_target!(
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init_target!(
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llvm_component = "mips",
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llvm_component = "mips",
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LLVMInitializeMipsTargetInfo,
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LLVMInitializeMipsTargetInfo,
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@ -88,7 +88,7 @@ changelog-seen = 2
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# the resulting rustc being unable to compile for the disabled architectures.
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# the resulting rustc being unable to compile for the disabled architectures.
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#
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#
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# To add support for new targets, see https://rustc-dev-guide.rust-lang.org/building/new-target.html.
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# To add support for new targets, see https://rustc-dev-guide.rust-lang.org/building/new-target.html.
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#targets = "AArch64;ARM;BPF;Hexagon;MSP430;Mips;NVPTX;PowerPC;RISCV;Sparc;SystemZ;WebAssembly;X86"
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#targets = "AArch64;ARM;BPF;Hexagon;LoongArch;MSP430;Mips;NVPTX;PowerPC;RISCV;Sparc;SystemZ;WebAssembly;X86"
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# LLVM experimental targets to build support for. These targets are specified in
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# LLVM experimental targets to build support for. These targets are specified in
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# the same format as above, but since these targets are experimental, they are
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# the same format as above, but since these targets are experimental, they are
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@ -291,7 +291,7 @@ impl Step for Llvm {
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let llvm_targets = match &builder.config.llvm_targets {
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let llvm_targets = match &builder.config.llvm_targets {
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Some(s) => s,
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Some(s) => s,
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None => {
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None => {
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"AArch64;ARM;BPF;Hexagon;MSP430;Mips;NVPTX;PowerPC;RISCV;\
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"AArch64;ARM;BPF;Hexagon;LoongArch;MSP430;Mips;NVPTX;PowerPC;RISCV;\
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Sparc;SystemZ;WebAssembly;X86"
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Sparc;SystemZ;WebAssembly;X86"
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}
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}
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};
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};
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