Slight shaving on RA, no more optimizing today. It's fast enough for now.
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1 changed files with 9 additions and 8 deletions
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@ -190,11 +190,14 @@ let calculate_live_bitvectors
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let n_quads = Array.length quads in
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let n_vregs = cx.ctxt_n_vregs in
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let new_bitv _ = Bits.create n_vregs false in
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let new_true_bitv _ = Bits.create n_vregs true in
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let (live_in_vregs:Bits.t array) = Array.init n_quads new_bitv in
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let (live_out_vregs:Bits.t array) = Array.init n_quads new_bitv in
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let (quad_used_vrs:Bits.t array) = Array.init n_quads new_bitv in
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let (quad_defined_vrs:Bits.t array) = Array.init n_quads new_bitv in
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let (quad_not_defined_vrs:Bits.t array) =
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Array.init n_quads new_true_bitv
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in
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let (quad_uncond_jmp:bool array) = Array.make n_quads false in
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let (quad_jmp_targs:(Il.label list) array) = Array.make n_quads [] in
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@ -212,8 +215,8 @@ let calculate_live_bitvectors
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(fun v -> Bits.set quad_used_vrs.(i) v true)
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(quad_used_vregs q);
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List.iter
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(fun v -> Bits.set quad_defined_vrs.(i) v true)
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(quad_defined_vregs q)
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(fun v -> Bits.set quad_not_defined_vrs.(i) v false)
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(quad_defined_vregs q);
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done;
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while !changed do
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@ -228,7 +231,7 @@ let calculate_live_bitvectors
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let live_in = live_in_vregs.(i) in
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let live_out = live_out_vregs.(i) in
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let used = quad_used_vrs.(i) in
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let defined = quad_defined_vrs.(i) in
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let not_defined = quad_not_defined_vrs.(i) in
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(* Union in the vregs we use. *)
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note_change (Bits.union live_in used);
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@ -243,8 +246,7 @@ let calculate_live_bitvectors
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then note_change (Bits.union live_out live_in_vregs.(i+1));
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(* Propagate live-out to live-in on anything we don't define. *)
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ignore (Bits.copy scratch defined);
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Bits.invert scratch;
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ignore (Bits.copy scratch not_defined);
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ignore (Bits.intersect scratch live_out);
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note_change (Bits.union live_in scratch);
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@ -379,8 +381,7 @@ let reg_alloc
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let n_pre_spills = convert_pre_spills cx spill_slot in
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let (live_in_vregs, live_out_vregs) =
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Session.time_inner "RA liveness" sess
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(fun _ -> calculate_live_bitvectors cx)
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calculate_live_bitvectors cx
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in
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let (vreg_constraints:Bits.t array) = (* vreg idx -> hreg bits.t *)
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calculate_vreg_constraints cx
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