Add initial asm!() support for PowerPC
This includes GPRs and FPRs only
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Dr. Chat
parent
5c02926546
commit
b1bb5d662c
6 changed files with 356 additions and 1 deletions
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@ -154,6 +154,7 @@ mod arm;
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mod hexagon;
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mod mips;
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mod nvptx;
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mod powerpc;
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mod riscv;
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mod spirv;
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mod wasm;
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@ -164,6 +165,7 @@ pub use arm::{ArmInlineAsmReg, ArmInlineAsmRegClass};
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pub use hexagon::{HexagonInlineAsmReg, HexagonInlineAsmRegClass};
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pub use mips::{MipsInlineAsmReg, MipsInlineAsmRegClass};
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pub use nvptx::{NvptxInlineAsmReg, NvptxInlineAsmRegClass};
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pub use powerpc::{PowerPCInlineAsmReg, PowerPCInlineAsmRegClass};
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pub use riscv::{RiscVInlineAsmReg, RiscVInlineAsmRegClass};
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pub use spirv::{SpirVInlineAsmReg, SpirVInlineAsmRegClass};
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pub use wasm::{WasmInlineAsmReg, WasmInlineAsmRegClass};
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@ -181,6 +183,7 @@ pub enum InlineAsmArch {
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Hexagon,
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Mips,
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Mips64,
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PowerPC,
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SpirV,
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Wasm32,
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}
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@ -197,6 +200,7 @@ impl FromStr for InlineAsmArch {
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"riscv32" => Ok(Self::RiscV32),
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"riscv64" => Ok(Self::RiscV64),
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"nvptx64" => Ok(Self::Nvptx64),
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"powerpc" => Ok(Self::PowerPC),
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"hexagon" => Ok(Self::Hexagon),
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"mips" => Ok(Self::Mips),
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"mips64" => Ok(Self::Mips64),
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@ -225,6 +229,7 @@ pub enum InlineAsmReg {
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AArch64(AArch64InlineAsmReg),
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RiscV(RiscVInlineAsmReg),
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Nvptx(NvptxInlineAsmReg),
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PowerPC(PowerPCInlineAsmReg),
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Hexagon(HexagonInlineAsmReg),
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Mips(MipsInlineAsmReg),
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SpirV(SpirVInlineAsmReg),
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@ -240,6 +245,7 @@ impl InlineAsmReg {
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Self::Arm(r) => r.name(),
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Self::AArch64(r) => r.name(),
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Self::RiscV(r) => r.name(),
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Self::PowerPC(r) => r.name(),
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Self::Hexagon(r) => r.name(),
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Self::Mips(r) => r.name(),
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Self::Err => "<reg>",
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@ -252,6 +258,7 @@ impl InlineAsmReg {
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Self::Arm(r) => InlineAsmRegClass::Arm(r.reg_class()),
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Self::AArch64(r) => InlineAsmRegClass::AArch64(r.reg_class()),
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Self::RiscV(r) => InlineAsmRegClass::RiscV(r.reg_class()),
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Self::PowerPC(r) => InlineAsmRegClass::PowerPC(r.reg_class()),
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Self::Hexagon(r) => InlineAsmRegClass::Hexagon(r.reg_class()),
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Self::Mips(r) => InlineAsmRegClass::Mips(r.reg_class()),
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Self::Err => InlineAsmRegClass::Err,
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@ -283,6 +290,9 @@ impl InlineAsmReg {
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InlineAsmArch::Nvptx64 => {
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Self::Nvptx(NvptxInlineAsmReg::parse(arch, has_feature, target, &name)?)
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}
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InlineAsmArch::PowerPC => {
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Self::PowerPC(PowerPCInlineAsmReg::parse(arch, has_feature, target, &name)?)
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}
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InlineAsmArch::Hexagon => {
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Self::Hexagon(HexagonInlineAsmReg::parse(arch, has_feature, target, &name)?)
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}
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@ -311,6 +321,7 @@ impl InlineAsmReg {
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Self::Arm(r) => r.emit(out, arch, modifier),
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Self::AArch64(r) => r.emit(out, arch, modifier),
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Self::RiscV(r) => r.emit(out, arch, modifier),
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Self::PowerPC(r) => r.emit(out, arch, modifier),
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Self::Hexagon(r) => r.emit(out, arch, modifier),
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Self::Mips(r) => r.emit(out, arch, modifier),
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Self::Err => unreachable!("Use of InlineAsmReg::Err"),
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@ -323,6 +334,7 @@ impl InlineAsmReg {
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Self::Arm(r) => r.overlapping_regs(|r| cb(Self::Arm(r))),
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Self::AArch64(_) => cb(self),
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Self::RiscV(_) => cb(self),
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Self::PowerPC(_) => cb(self),
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Self::Hexagon(r) => r.overlapping_regs(|r| cb(Self::Hexagon(r))),
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Self::Mips(_) => cb(self),
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Self::Err => unreachable!("Use of InlineAsmReg::Err"),
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@ -348,6 +360,7 @@ pub enum InlineAsmRegClass {
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AArch64(AArch64InlineAsmRegClass),
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RiscV(RiscVInlineAsmRegClass),
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Nvptx(NvptxInlineAsmRegClass),
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PowerPC(PowerPCInlineAsmRegClass),
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Hexagon(HexagonInlineAsmRegClass),
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Mips(MipsInlineAsmRegClass),
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SpirV(SpirVInlineAsmRegClass),
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@ -364,6 +377,7 @@ impl InlineAsmRegClass {
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Self::AArch64(r) => r.name(),
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Self::RiscV(r) => r.name(),
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Self::Nvptx(r) => r.name(),
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Self::PowerPC(r) => r.name(),
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Self::Hexagon(r) => r.name(),
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Self::Mips(r) => r.name(),
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Self::SpirV(r) => r.name(),
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@ -382,6 +396,7 @@ impl InlineAsmRegClass {
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Self::AArch64(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::AArch64),
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Self::RiscV(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::RiscV),
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Self::Nvptx(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Nvptx),
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Self::PowerPC(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::PowerPC),
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Self::Hexagon(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Hexagon),
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Self::Mips(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Mips),
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Self::SpirV(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::SpirV),
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@ -407,6 +422,7 @@ impl InlineAsmRegClass {
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Self::AArch64(r) => r.suggest_modifier(arch, ty),
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Self::RiscV(r) => r.suggest_modifier(arch, ty),
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Self::Nvptx(r) => r.suggest_modifier(arch, ty),
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Self::PowerPC(r) => r.suggest_modifier(arch, ty),
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Self::Hexagon(r) => r.suggest_modifier(arch, ty),
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Self::Mips(r) => r.suggest_modifier(arch, ty),
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Self::SpirV(r) => r.suggest_modifier(arch, ty),
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@ -428,6 +444,7 @@ impl InlineAsmRegClass {
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Self::AArch64(r) => r.default_modifier(arch),
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Self::RiscV(r) => r.default_modifier(arch),
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Self::Nvptx(r) => r.default_modifier(arch),
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Self::PowerPC(r) => r.default_modifier(arch),
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Self::Hexagon(r) => r.default_modifier(arch),
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Self::Mips(r) => r.default_modifier(arch),
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Self::SpirV(r) => r.default_modifier(arch),
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@ -448,6 +465,7 @@ impl InlineAsmRegClass {
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Self::AArch64(r) => r.supported_types(arch),
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Self::RiscV(r) => r.supported_types(arch),
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Self::Nvptx(r) => r.supported_types(arch),
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Self::PowerPC(r) => r.supported_types(arch),
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Self::Hexagon(r) => r.supported_types(arch),
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Self::Mips(r) => r.supported_types(arch),
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Self::SpirV(r) => r.supported_types(arch),
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@ -467,6 +485,7 @@ impl InlineAsmRegClass {
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Self::RiscV(RiscVInlineAsmRegClass::parse(arch, name)?)
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}
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InlineAsmArch::Nvptx64 => Self::Nvptx(NvptxInlineAsmRegClass::parse(arch, name)?),
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InlineAsmArch::PowerPC => Self::PowerPC(PowerPCInlineAsmRegClass::parse(arch, name)?),
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InlineAsmArch::Hexagon => Self::Hexagon(HexagonInlineAsmRegClass::parse(arch, name)?),
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InlineAsmArch::Mips | InlineAsmArch::Mips64 => {
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Self::Mips(MipsInlineAsmRegClass::parse(arch, name)?)
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@ -485,6 +504,7 @@ impl InlineAsmRegClass {
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Self::AArch64(r) => r.valid_modifiers(arch),
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Self::RiscV(r) => r.valid_modifiers(arch),
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Self::Nvptx(r) => r.valid_modifiers(arch),
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Self::PowerPC(r) => r.valid_modifiers(arch),
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Self::Hexagon(r) => r.valid_modifiers(arch),
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Self::Mips(r) => r.valid_modifiers(arch),
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Self::SpirV(r) => r.valid_modifiers(arch),
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@ -633,6 +653,11 @@ pub fn allocatable_registers(
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nvptx::fill_reg_map(arch, has_feature, target, &mut map);
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map
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}
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InlineAsmArch::PowerPC => {
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let mut map = powerpc::regclass_map();
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powerpc::fill_reg_map(arch, has_feature, target, &mut map);
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map
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}
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InlineAsmArch::Hexagon => {
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let mut map = hexagon::regclass_map();
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hexagon::fill_reg_map(arch, has_feature, target, &mut map);
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