BPF: misc minor review fixes
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5 changed files with 11 additions and 11 deletions
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@ -12,6 +12,10 @@ pub fn opts(endian: Endian) -> TargetOptions {
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no_builtins: true,
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no_builtins: true,
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panic_strategy: PanicStrategy::Abort,
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panic_strategy: PanicStrategy::Abort,
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position_independent_executables: true,
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position_independent_executables: true,
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// Disable MergeFunctions since:
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// - older kernels don't support bpf-to-bpf calls
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// - on newer kernels, userspace still needs to relocate before calling
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// BPF_PROG_LOAD and not all BPF libraries do that yet
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merge_functions: MergeFunctions::Disabled,
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merge_functions: MergeFunctions::Disabled,
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obj_is_bitcode: true,
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obj_is_bitcode: true,
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requires_lto: false,
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requires_lto: false,
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@ -235,8 +235,8 @@ impl Step for Llvm {
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let llvm_targets = match &builder.config.llvm_targets {
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let llvm_targets = match &builder.config.llvm_targets {
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Some(s) => s,
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Some(s) => s,
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None => {
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None => {
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"AArch64;ARM;Hexagon;MSP430;Mips;NVPTX;PowerPC;RISCV;\
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"AArch64;ARM;BPF;Hexagon;MSP430;Mips;NVPTX;PowerPC;RISCV;\
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Sparc;SystemZ;WebAssembly;X86;BPF"
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Sparc;SystemZ;WebAssembly;X86"
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}
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}
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};
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};
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@ -571,8 +571,8 @@ Here is the list of currently supported register classes:
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| PowerPC | `reg_nonzero` | | `r[1-31]` | `b` |
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| PowerPC | `reg_nonzero` | | `r[1-31]` | `b` |
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| PowerPC | `freg` | `f[0-31]` | `f` |
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| PowerPC | `freg` | `f[0-31]` | `f` |
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| wasm32 | `local` | None\* | `r` |
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| wasm32 | `local` | None\* | `r` |
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| BPF | `reg` | `r[0-10]` | `r`|
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| BPF | `reg` | `r[0-10]` | `r` |
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| BPF | `wreg` | `w[0-10]` | `w`|
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| BPF | `wreg` | `w[0-10]` | `w` |
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> **Note**: On x86 we treat `reg_byte` differently from `reg` because the compiler can allocate `al` and `ah` separately whereas `reg` reserves the whole register.
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> **Note**: On x86 we treat `reg_byte` differently from `reg` because the compiler can allocate `al` and `ah` separately whereas `reg` reserves the whole register.
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>
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>
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@ -619,7 +619,7 @@ Each register class has constraints on which value types they can be used with.
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| PowerPC | `freg` | None | `f32`, `f64` |
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| PowerPC | `freg` | None | `f32`, `f64` |
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| wasm32 | `local` | None | `i8` `i16` `i32` `i64` `f32` `f64` |
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| wasm32 | `local` | None | `i8` `i16` `i32` `i64` `f32` `f64` |
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| BPF | `reg` | None | `i8` `i16` `i32` `i64` |
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| BPF | `reg` | None | `i8` `i16` `i32` `i64` |
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| BPF | `wreg` | `alu32` | `i8` `i16` `i32`|
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| BPF | `wreg` | `alu32` | `i8` `i16` `i32` |
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> **Note**: For the purposes of the above table pointers, function pointers and `isize`/`usize` are treated as the equivalent integer type (`i16`/`i32`/`i64` depending on the target).
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> **Note**: For the purposes of the above table pointers, function pointers and `isize`/`usize` are treated as the equivalent integer type (`i16`/`i32`/`i64` depending on the target).
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@ -2311,10 +2311,6 @@ impl<'test> TestCx<'test> {
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// No extra flags needed.
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// No extra flags needed.
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}
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}
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Some("bpf-linker") => {
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rustc.arg("-Clink-args=--emit=asm");
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}
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Some(_) => self.fatal("unknown 'assembly-output' header"),
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Some(_) => self.fatal("unknown 'assembly-output' header"),
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None => self.fatal("missing 'assembly-output' header"),
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None => self.fatal("missing 'assembly-output' header"),
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}
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}
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@ -48,8 +48,8 @@ const ARCH_TABLE: &[(&str, &str)] = &[
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("armv7s", "arm"),
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("armv7s", "arm"),
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("asmjs", "asmjs"),
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("asmjs", "asmjs"),
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("avr", "avr"),
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("avr", "avr"),
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("bpfeb", "bpfeb"),
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("bpfeb", "bpf"),
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("bpfel", "bpfel"),
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("bpfel", "bpf"),
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("hexagon", "hexagon"),
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("hexagon", "hexagon"),
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("i386", "x86"),
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("i386", "x86"),
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("i586", "x86"),
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("i586", "x86"),
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