rename BackendRepr::Vector → SimdVector
This commit is contained in:
Ralf Jung
parent
2f581937e1
commit
aac65f562b
32 changed files with 92 additions and 83 deletions
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@ -939,9 +939,10 @@ fn llvm_fixup_input<'ll, 'tcx>(
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}
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bx.insert_element(bx.const_undef(vec_ty), value, bx.const_i32(0))
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}
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(AArch64(AArch64InlineAsmRegClass::vreg_low16), BackendRepr::Vector { element, count })
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if layout.size.bytes() == 8 =>
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{
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(
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AArch64(AArch64InlineAsmRegClass::vreg_low16),
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BackendRepr::SimdVector { element, count },
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) if layout.size.bytes() == 8 => {
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let elem_ty = llvm_asm_scalar_type(bx.cx, element);
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let vec_ty = bx.cx.type_vector(elem_ty, count);
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let indices: Vec<_> = (0..count * 2).map(|x| bx.const_i32(x as i32)).collect();
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@ -954,7 +955,7 @@ fn llvm_fixup_input<'ll, 'tcx>(
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}
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(
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X86(X86InlineAsmRegClass::xmm_reg | X86InlineAsmRegClass::zmm_reg),
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BackendRepr::Vector { .. },
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BackendRepr::SimdVector { .. },
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) if layout.size.bytes() == 64 => bx.bitcast(value, bx.cx.type_vector(bx.cx.type_f64(), 8)),
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(
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X86(
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@ -989,7 +990,7 @@ fn llvm_fixup_input<'ll, 'tcx>(
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| X86InlineAsmRegClass::ymm_reg
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| X86InlineAsmRegClass::zmm_reg,
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),
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BackendRepr::Vector { element, count: count @ (8 | 16) },
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BackendRepr::SimdVector { element, count: count @ (8 | 16) },
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) if element.primitive() == Primitive::Float(Float::F16) => {
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bx.bitcast(value, bx.type_vector(bx.type_i16(), count))
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}
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@ -1026,7 +1027,7 @@ fn llvm_fixup_input<'ll, 'tcx>(
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| ArmInlineAsmRegClass::qreg_low4
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| ArmInlineAsmRegClass::qreg_low8,
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),
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BackendRepr::Vector { element, count: count @ (4 | 8) },
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BackendRepr::SimdVector { element, count: count @ (4 | 8) },
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) if element.primitive() == Primitive::Float(Float::F16) => {
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bx.bitcast(value, bx.type_vector(bx.type_i16(), count))
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}
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@ -1099,9 +1100,10 @@ fn llvm_fixup_output<'ll, 'tcx>(
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}
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value
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}
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(AArch64(AArch64InlineAsmRegClass::vreg_low16), BackendRepr::Vector { element, count })
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if layout.size.bytes() == 8 =>
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{
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(
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AArch64(AArch64InlineAsmRegClass::vreg_low16),
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BackendRepr::SimdVector { element, count },
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) if layout.size.bytes() == 8 => {
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let elem_ty = llvm_asm_scalar_type(bx.cx, element);
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let vec_ty = bx.cx.type_vector(elem_ty, count * 2);
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let indices: Vec<_> = (0..count).map(|x| bx.const_i32(x as i32)).collect();
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@ -1114,7 +1116,7 @@ fn llvm_fixup_output<'ll, 'tcx>(
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}
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(
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X86(X86InlineAsmRegClass::xmm_reg | X86InlineAsmRegClass::zmm_reg),
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BackendRepr::Vector { .. },
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BackendRepr::SimdVector { .. },
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) if layout.size.bytes() == 64 => bx.bitcast(value, layout.llvm_type(bx.cx)),
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(
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X86(
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@ -1145,7 +1147,7 @@ fn llvm_fixup_output<'ll, 'tcx>(
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| X86InlineAsmRegClass::ymm_reg
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| X86InlineAsmRegClass::zmm_reg,
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),
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BackendRepr::Vector { element, count: count @ (8 | 16) },
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BackendRepr::SimdVector { element, count: count @ (8 | 16) },
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) if element.primitive() == Primitive::Float(Float::F16) => {
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bx.bitcast(value, bx.type_vector(bx.type_f16(), count))
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}
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@ -1182,7 +1184,7 @@ fn llvm_fixup_output<'ll, 'tcx>(
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| ArmInlineAsmRegClass::qreg_low4
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| ArmInlineAsmRegClass::qreg_low8,
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),
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BackendRepr::Vector { element, count: count @ (4 | 8) },
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BackendRepr::SimdVector { element, count: count @ (4 | 8) },
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) if element.primitive() == Primitive::Float(Float::F16) => {
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bx.bitcast(value, bx.type_vector(bx.type_f16(), count))
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}
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@ -1243,9 +1245,10 @@ fn llvm_fixup_output_type<'ll, 'tcx>(
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let count = 16 / layout.size.bytes();
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cx.type_vector(elem_ty, count)
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}
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(AArch64(AArch64InlineAsmRegClass::vreg_low16), BackendRepr::Vector { element, count })
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if layout.size.bytes() == 8 =>
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{
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(
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AArch64(AArch64InlineAsmRegClass::vreg_low16),
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BackendRepr::SimdVector { element, count },
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) if layout.size.bytes() == 8 => {
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let elem_ty = llvm_asm_scalar_type(cx, element);
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cx.type_vector(elem_ty, count * 2)
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}
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@ -1256,7 +1259,7 @@ fn llvm_fixup_output_type<'ll, 'tcx>(
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}
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(
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X86(X86InlineAsmRegClass::xmm_reg | X86InlineAsmRegClass::zmm_reg),
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BackendRepr::Vector { .. },
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BackendRepr::SimdVector { .. },
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) if layout.size.bytes() == 64 => cx.type_vector(cx.type_f64(), 8),
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(
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X86(
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@ -1284,7 +1287,7 @@ fn llvm_fixup_output_type<'ll, 'tcx>(
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| X86InlineAsmRegClass::ymm_reg
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| X86InlineAsmRegClass::zmm_reg,
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),
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BackendRepr::Vector { element, count: count @ (8 | 16) },
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BackendRepr::SimdVector { element, count: count @ (8 | 16) },
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) if element.primitive() == Primitive::Float(Float::F16) => {
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cx.type_vector(cx.type_i16(), count)
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}
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@ -1321,7 +1324,7 @@ fn llvm_fixup_output_type<'ll, 'tcx>(
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| ArmInlineAsmRegClass::qreg_low4
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| ArmInlineAsmRegClass::qreg_low8,
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),
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BackendRepr::Vector { element, count: count @ (4 | 8) },
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BackendRepr::SimdVector { element, count: count @ (4 | 8) },
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) if element.primitive() == Primitive::Float(Float::F16) => {
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cx.type_vector(cx.type_i16(), count)
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}
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@ -470,7 +470,7 @@ impl<'ll, 'tcx> IntrinsicCallBuilderMethods<'tcx> for Builder<'_, 'll, 'tcx> {
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let layout = self.layout_of(tp_ty).layout;
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let use_integer_compare = match layout.backend_repr() {
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Scalar(_) | ScalarPair(_, _) => true,
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Vector { .. } => false,
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SimdVector { .. } => false,
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Memory { .. } => {
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// For rusty ABIs, small aggregates are actually passed
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// as `RegKind::Integer` (see `FnAbi::adjust_for_abi`),
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@ -19,7 +19,7 @@ fn uncached_llvm_type<'a, 'tcx>(
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) -> &'a Type {
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match layout.backend_repr {
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BackendRepr::Scalar(_) => bug!("handled elsewhere"),
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BackendRepr::Vector { element, count } => {
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BackendRepr::SimdVector { element, count } => {
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let element = layout.scalar_llvm_type_at(cx, element);
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return cx.type_vector(element, count);
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}
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@ -171,7 +171,7 @@ pub(crate) trait LayoutLlvmExt<'tcx> {
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impl<'tcx> LayoutLlvmExt<'tcx> for TyAndLayout<'tcx> {
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fn is_llvm_immediate(&self) -> bool {
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match self.backend_repr {
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BackendRepr::Scalar(_) | BackendRepr::Vector { .. } => true,
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BackendRepr::Scalar(_) | BackendRepr::SimdVector { .. } => true,
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BackendRepr::ScalarPair(..) | BackendRepr::Memory { .. } => false,
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}
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}
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@ -179,9 +179,9 @@ impl<'tcx> LayoutLlvmExt<'tcx> for TyAndLayout<'tcx> {
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fn is_llvm_scalar_pair(&self) -> bool {
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match self.backend_repr {
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BackendRepr::ScalarPair(..) => true,
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BackendRepr::Scalar(_) | BackendRepr::Vector { .. } | BackendRepr::Memory { .. } => {
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false
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}
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BackendRepr::Scalar(_)
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| BackendRepr::SimdVector { .. }
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| BackendRepr::Memory { .. } => false,
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}
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}
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