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Merge pull request #1564 from rust-lang/fix_arm64_asm_vector_regs

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Fix usage of vector registers in inline asm on arm64
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bjorn3 2025-03-16 18:01:11 +01:00 • committed by GitHub
commit 92e5c1a44d
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1 changed files with 28 additions and 2 deletions
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30
src/inline_asm.rs
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@ -652,6 +652,20 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> {
.emit(&mut generated_asm, InlineAsmArch::X86_64, *modifier) .emit(&mut generated_asm, InlineAsmArch::X86_64, *modifier)
.unwrap(), .unwrap(),
}, },
InlineAsmArch::AArch64 => match reg {
InlineAsmReg::AArch64(reg) if reg.vreg_index().is_some() => {
// rustc emits v0 rather than q0
reg.emit(
&mut generated_asm,
InlineAsmArch::AArch64,
Some(modifier.unwrap_or('q')),
)
.unwrap()
}
_ => reg
.emit(&mut generated_asm, InlineAsmArch::AArch64, *modifier)
.unwrap(),
},
_ => reg.emit(&mut generated_asm, self.arch, *modifier).unwrap(), _ => reg.emit(&mut generated_asm, self.arch, *modifier).unwrap(),
} }
} }
@ -809,7 +823,13 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> {
} }
InlineAsmArch::AArch64 => { InlineAsmArch::AArch64 => {
generated_asm.push_str(" str "); generated_asm.push_str(" str ");
reg.emit(generated_asm, InlineAsmArch::AArch64, None).unwrap(); match reg {
InlineAsmReg::AArch64(reg) if reg.vreg_index().is_some() => {
// rustc emits v0 rather than q0
reg.emit(generated_asm, InlineAsmArch::AArch64, Some('q')).unwrap()
}
_ => reg.emit(generated_asm, InlineAsmArch::AArch64, None).unwrap(),
}
writeln!(generated_asm, ", [x19, 0x{:x}]", offset.bytes()).unwrap(); writeln!(generated_asm, ", [x19, 0x{:x}]", offset.bytes()).unwrap();
} }
InlineAsmArch::RiscV64 => { InlineAsmArch::RiscV64 => {
@ -851,7 +871,13 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> {
} }
InlineAsmArch::AArch64 => { InlineAsmArch::AArch64 => {
generated_asm.push_str(" ldr "); generated_asm.push_str(" ldr ");
reg.emit(generated_asm, InlineAsmArch::AArch64, None).unwrap(); match reg {
InlineAsmReg::AArch64(reg) if reg.vreg_index().is_some() => {
// rustc emits v0 rather than q0
reg.emit(generated_asm, InlineAsmArch::AArch64, Some('q')).unwrap()
}
_ => reg.emit(generated_asm, InlineAsmArch::AArch64, None).unwrap(),
}
writeln!(generated_asm, ", [x19, 0x{:x}]", offset.bytes()).unwrap(); writeln!(generated_asm, ", [x19, 0x{:x}]", offset.bytes()).unwrap();
} }
InlineAsmArch::RiscV64 => { InlineAsmArch::RiscV64 => {