bjoernager/rust
bjoernager/rust
1
Fork 0
Code Activity

Only check for successful vectorization on wider_reduce_into_iter

Browse source 
Different vectorization results are due to different LLVM versions.
This commit is contained in:
DianQK 2023-09-24 09:46:04 +08:00
parent d30f210e5d
commit 910674f1c4
No known key found for this signature in database
GPG key ID: 46BDB1AC96C48912
1 changed files with 1 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

4
tests/codegen/simd/simd-wide-sum.rs
View file

@ -52,8 +52,6 @@ pub fn wider_reduce_iter(x: Simd<u8, N>) -> u16 {
#[no_mangle] #[no_mangle]
// CHECK-LABEL: @wider_reduce_into_iter // CHECK-LABEL: @wider_reduce_into_iter
pub fn wider_reduce_into_iter(x: Simd<u8, N>) -> u16 { pub fn wider_reduce_into_iter(x: Simd<u8, N>) -> u16 {
// CHECK: zext <16 x i8> // CHECK: call i16 @llvm.vector.reduce.add
// CHECK-SAME: to <16 x i16>
// CHECK: call i16 @llvm.vector.reduce.add.v16i16(<16 x i16>
x.to_array().into_iter().map(u16::from).sum() x.to_array().into_iter().map(u16::from).sum()
} }