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Auto merge of #98333 - SimonSapin:riscv-atomic, r=Amanieu

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Re-enable atomic loads and stores for all RISC-V targets

This roughly reverts PR https://github.com/rust-lang/rust/pull/66548

Atomic "CAS" are still disabled for targets without the *“A” Standard Extension for Atomic Instructions*. However this extension only adds instructions for operations more complex than simple loads and stores, which are always atomic when aligned.

In the [Unprivileged Spec v. 20191213](https://riscv.org/technical/specifications/) section 2.6 *Load and Store Instructions* of chapter 2 *RV32I Base Integer Instruction Set* (emphasis mine):

> Even when misaligned loads and stores complete successfully, these accesses might run extremely slowly depending on the implementation (e.g., when implemented via an invisible trap). Further-more, whereas **naturally aligned loads and stores are guaranteed to execute atomically**, misaligned loads and stores might not, and hence require additional synchronization to ensure atomicity.

Unfortunately PR https://github.com/rust-lang/rust/pull/66548 did not provide much details on the bug that motivated it, but https://github.com/rust-lang/rust/issues/66240 and https://github.com/rust-lang/rust/issues/85736 appear related and happen with targets that do have the A extension.
This commit is contained in:
bors 2023-08-05 01:53:32 +00:00
commit 90f0b24ad3
3 changed files with 3 additions and 3 deletions
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2
compiler/rustc_target/src/spec/riscv32i_unknown_none_elf.rs
View file

@ -11,7 +11,7 @@ pub fn target() -> Target {
linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes), linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
linker: Some("rust-lld".into()), linker: Some("rust-lld".into()),
cpu: "generic-rv32".into(), cpu: "generic-rv32".into(),
max_atomic_width: Some(0), max_atomic_width: Some(32),
atomic_cas: false, atomic_cas: false,
panic_strategy: PanicStrategy::Abort, panic_strategy: PanicStrategy::Abort,
relocation_model: RelocModel::Static, relocation_model: RelocModel::Static,

2
compiler/rustc_target/src/spec/riscv32im_unknown_none_elf.rs
View file

@ -11,7 +11,7 @@ pub fn target() -> Target {
linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes), linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
linker: Some("rust-lld".into()), linker: Some("rust-lld".into()),
cpu: "generic-rv32".into(), cpu: "generic-rv32".into(),
max_atomic_width: Some(0), max_atomic_width: Some(32),
atomic_cas: false, atomic_cas: false,
features: "+m".into(), features: "+m".into(),
panic_strategy: PanicStrategy::Abort, panic_strategy: PanicStrategy::Abort,

2
compiler/rustc_target/src/spec/riscv32imc_unknown_none_elf.rs
View file

@ -11,7 +11,7 @@ pub fn target() -> Target {
linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes), linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
linker: Some("rust-lld".into()), linker: Some("rust-lld".into()),
cpu: "generic-rv32".into(), cpu: "generic-rv32".into(),
max_atomic_width: Some(0), max_atomic_width: Some(32),
atomic_cas: false, atomic_cas: false,
features: "+m,+c".into(), features: "+m,+c".into(),
panic_strategy: PanicStrategy::Abort, panic_strategy: PanicStrategy::Abort,