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Remove the reg_thumb register class for asm! on ARM

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Also restricts r8-r14 from being used on Thumb1 targets as per #90736.
This commit is contained in:
Amanieu d'Antras 2021-11-11 12:42:38 +00:00
parent 0b6f079e49
commit 908f300dd7
8 changed files with 30 additions and 65 deletions
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37
compiler/rustc_target/src/asm/arm.rs
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@ -6,7 +6,6 @@ use std::fmt;
def_reg_class! {
Arm ArmInlineAsmRegClass {
reg,
reg_thumb,
sreg,
sreg_low16,
dreg,
@ -47,7 +46,7 @@ impl ArmInlineAsmRegClass {
_arch: InlineAsmArch,
) -> &'static [(InlineAsmType, Option<&'static str>)] {
match self {
Self::reg | Self::reg_thumb => types! { _: I8, I16, I32, F32; },
Self::reg => types! { _: I8, I16, I32, F32; },
Self::sreg | Self::sreg_low16 => types! { "vfp2": I32, F32; },
Self::dreg | Self::dreg_low16 | Self::dreg_low8 => types! {
"vfp2": I64, F64, VecI8(8), VecI16(4), VecI32(2), VecI64(1), VecF32(2);
@ -88,20 +87,32 @@ fn frame_pointer_r7(
}
}
fn not_thumb1(
_arch: InlineAsmArch,
mut has_feature: impl FnMut(&str) -> bool,
_target: &Target,
) -> Result<(), &'static str> {
if has_feature("thumb-mode") && !has_feature("thumb2") {
Err("high registers (r8+) cannot be used in Thumb-1 code")
} else {
Ok(())
}
}
def_regs! {
Arm ArmInlineAsmReg ArmInlineAsmRegClass {
r0: reg, reg_thumb = ["r0", "a1"],
r1: reg, reg_thumb = ["r1", "a2"],
r2: reg, reg_thumb = ["r2", "a3"],
r3: reg, reg_thumb = ["r3", "a4"],
r4: reg, reg_thumb = ["r4", "v1"],
r5: reg, reg_thumb = ["r5", "v2"],
r7: reg, reg_thumb = ["r7", "v4"] % frame_pointer_r7,
r8: reg = ["r8", "v5"],
r10: reg = ["r10", "sl"],
r0: reg = ["r0", "a1"],
r1: reg = ["r1", "a2"],
r2: reg = ["r2", "a3"],
r3: reg = ["r3", "a4"],
r4: reg = ["r4", "v1"],
r5: reg = ["r5", "v2"],
r7: reg = ["r7", "v4"] % frame_pointer_r7,
r8: reg = ["r8", "v5"] % not_thumb1,
r10: reg = ["r10", "sl"] % not_thumb1,
r11: reg = ["r11", "fp"] % frame_pointer_r11,
r12: reg = ["r12", "ip"],
r14: reg = ["r14", "lr"],
r12: reg = ["r12", "ip"] % not_thumb1,
r14: reg = ["r14", "lr"] % not_thumb1,
s0: sreg, sreg_low16 = ["s0"],
s1: sreg, sreg_low16 = ["s1"],
s2: sreg, sreg_low16 = ["s2"],