Auto merge of #138742 - taiki-e:riscv-vector, r=Amanieu

rustc_target: Add more RISC-V vector-related features and use zvl*b target features in vector ABI check

Currently, we have only unstable `v` target feature, but RISC-V have more vector-related extensions. The first commit of this PR adds them to unstable `riscv_target_feature`.

- `unaligned-vector-mem`: Has reasonably performant unaligned vector
  - [LLVM definition](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L1379)
  - Similar to currently unstable `unaligned-scalar-mem` target feature, but for vector instructions.
- `zvfh`: Vector Extension for Half-Precision Floating-Point
  - [ISA Manual](https://github.com/riscv/riscv-isa-manual/blob/riscv-isa-release-2336fdc-2025-03-19/src/v-st-ext.adoc#zvfh-vector-extension-for-half-precision-floating-point)
  - [LLVM definition](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L668)
  - This implies `zvfhmin` and `zfhmin`
- `zvfhmin`: Vector Extension for Minimal Half-Precision Floating-Point
  - [ISA Manual](https://github.com/riscv/riscv-isa-manual/blob/riscv-isa-release-2336fdc-2025-03-19/src/v-st-ext.adoc#zvfhmin-vector-extension-for-minimal-half-precision-floating-point)
  - [LLVM definition](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L662)
  - This implies `zve32f`
- `zve32x`, `zve32f`, `zve64x`, `zve64f`, `zve64d`: Vector Extensions for Embedded Processors
  - [ISA Manual](https://github.com/riscv/riscv-isa-manual/blob/riscv-isa-release-2336fdc-2025-03-19/src/v-st-ext.adoc#zve-vector-extensions-for-embedded-processors)
  - [LLVM definitions](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L612-L641)
  - `zve32x` implies `zvl32b`
  - `zve32f` implies `zve32x` and `f`
  - `zve64x` implies `zve32x` and `zvl64b`
  - `zve64f` implies `zve32f` and `zve64x`
  - `zve64d` implies `zve64f` and `d`
  - `v` implies `zve64d`
- `zvl*b`: Minimum Vector Length Standard Extensions
  - [ISA Manual](https://github.com/riscv/riscv-isa-manual/blob/riscv-isa-release-2336fdc-2025-03-19/src/v-st-ext.adoc#zvl-minimum-vector-length-standard-extensions)
  - [LLVM definitions](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L600-L610)
  - `zvl{N}b` implies `zvl{N>>1}b`
  - `v` implies `zvl128b`
- Vector Cryptography and Bit-manipulation Extensions
  - [ISA Manual](https://github.com/riscv/riscv-isa-manual/blob/riscv-isa-release-2336fdc-2025-03-19/src/vector-crypto.adoc)
  - [LLVM definitions](https://github.com/llvm/llvm-project/blob/llvmorg-20.1.0/llvm/lib/Target/RISCV/RISCVFeatures.td#L679-L807)
  - `zvkb`: Vector Bit-manipulation used in Cryptography
    - This implies `zve32x`
  - `zvbb`: Vector basic bit-manipulation instructions
    - This implies `zvkb`
  - `zvbc`: Vector Carryless Multiplication
    - This implies `zve64x`
  - `zvkg`: Vector GCM instructions for Cryptography
    - This implies `zve32x`
  - `zvkned`: Vector AES Encryption & Decryption (Single Round)
    - This implies `zve32x`
  - `zvknha`: Vector SHA-2 (SHA-256 only))
    - This implies `zve32x`
  - `zvknhb`: Vector SHA-2 (SHA-256 and SHA-512)
    - This implies `zve64x`
    - This is superset of `zvknha`, but doesn't imply that feature at least in LLVM
  - `zvksed`: SM4 Block Cipher Instructions
    - This implies `zve32x`
  - `zvksh`: SM3 Hash Function Instructions
    - This implies `zve32x`
  - `zvkt`: Vector Data-Independent Execution Latency
    - Similar to already stabilized scalar cryptography extension `zkt`.
  - `zvkn`: Shorthand for 'Zvkned', 'Zvknhb', 'Zvkb', and 'Zvkt'
    - Similar to already stabilized scalar cryptography extension `zkn`.
  - `zvknc`: Shorthand for 'Zvkn' and 'Zvbc'
  - `zvkng`: shorthand for 'Zvkn' and 'Zvkg'
  - `zvks`: shorthand for 'Zvksed', 'Zvksh', 'Zvkb', and 'Zvkt'
    - Similar to already stabilized scalar cryptography extension `zks`.
  - `zvksc`: shorthand for 'Zvks' and 'Zvbc'
  - `zvksg`: shorthand for 'Zvks' and 'Zvkg'

Also, our vector ABI check wants `zvl*b` target features, the second commit of this PR updates vector ABI check to use them.

4e2b096ed6/compiler/rustc_target/src/target_features.rs (L707-L708)

---

r? `@Amanieu`

`@rustbot` label +O-riscv +A-target-feature

compiler/rustc_codegen_llvm/src/llvm_util.rs

@@ -274,7 +274,9 @@ pub(crate) fn to_llvm_features<'a>(sess: &Session, s: &'a str) -> Option<LLVMFea
         ("arm", "fp16") => Some(LLVMFeature::new("fullfp16")),
         // In LLVM 18, `unaligned-scalar-mem` was merged with `unaligned-vector-mem` into a single
         // feature called `fast-unaligned-access`. In LLVM 19, it was split back out.
-        ("riscv32" | "riscv64", "unaligned-scalar-mem") if get_version().0 == 18 => {
+        ("riscv32" | "riscv64", "unaligned-scalar-mem" | "unaligned-vector-mem")
+            if get_version().0 == 18 =>
+        {
             Some(LLVMFeature::new("fast-unaligned-access"))
         }
         // Filter out features that are not supported by the current LLVM version