Fix some warnings
This commit is contained in:
parent
7e6d533af2
commit
7564a043d0
4 changed files with 11 additions and 15 deletions
|
@ -86,7 +86,7 @@ pub fn codegen_llvm_intrinsic_call<'tcx>(
|
|||
kind => unreachable!("kind {:?}", kind),
|
||||
};
|
||||
|
||||
simd_pair_for_each_lane(fx, intrinsic, x, y, ret, |fx, lane_layout, res_lane_layout, x_lane, y_lane| {
|
||||
simd_pair_for_each_lane(fx, x, y, ret, |fx, lane_layout, res_lane_layout, x_lane, y_lane| {
|
||||
let res_lane = match lane_layout.ty.kind {
|
||||
ty::Float(_) => fx.bcx.ins().fcmp(flt_cc, x_lane, y_lane),
|
||||
_ => unreachable!("{:?}", lane_layout.ty),
|
||||
|
|
|
@ -145,7 +145,6 @@ pub fn lane_type_and_count<'tcx>(
|
|||
|
||||
fn simd_for_each_lane<'tcx, B: Backend>(
|
||||
fx: &mut FunctionCx<'_, 'tcx, B>,
|
||||
intrinsic: &str,
|
||||
val: CValue<'tcx>,
|
||||
ret: CPlace<'tcx>,
|
||||
f: impl Fn(
|
||||
|
@ -173,7 +172,6 @@ fn simd_for_each_lane<'tcx, B: Backend>(
|
|||
|
||||
fn simd_pair_for_each_lane<'tcx, B: Backend>(
|
||||
fx: &mut FunctionCx<'_, 'tcx, B>,
|
||||
intrinsic: &str,
|
||||
x: CValue<'tcx>,
|
||||
y: CValue<'tcx>,
|
||||
ret: CPlace<'tcx>,
|
||||
|
@ -231,10 +229,9 @@ fn bool_to_zero_or_max_uint<'tcx>(
|
|||
}
|
||||
|
||||
macro simd_cmp {
|
||||
($fx:expr, $intrinsic:expr, $cc:ident($x:ident, $y:ident) -> $ret:ident) => {
|
||||
($fx:expr, $cc:ident($x:ident, $y:ident) -> $ret:ident) => {
|
||||
simd_pair_for_each_lane(
|
||||
$fx,
|
||||
$intrinsic,
|
||||
$x,
|
||||
$y,
|
||||
$ret,
|
||||
|
@ -247,10 +244,9 @@ macro simd_cmp {
|
|||
},
|
||||
);
|
||||
},
|
||||
($fx:expr, $intrinsic:expr, $cc_u:ident|$cc_s:ident($x:ident, $y:ident) -> $ret:ident) => {
|
||||
($fx:expr, $cc_u:ident|$cc_s:ident($x:ident, $y:ident) -> $ret:ident) => {
|
||||
simd_pair_for_each_lane(
|
||||
$fx,
|
||||
$intrinsic,
|
||||
$x,
|
||||
$y,
|
||||
$ret,
|
||||
|
|
|
@ -21,7 +21,7 @@ pub fn codegen_simd_intrinsic_call<'tcx>(
|
|||
};
|
||||
|
||||
simd_cast, (c a) {
|
||||
simd_for_each_lane(fx, intrinsic, a, ret, |fx, lane_layout, ret_lane_layout, lane| {
|
||||
simd_for_each_lane(fx, a, ret, |fx, lane_layout, ret_lane_layout, lane| {
|
||||
let ret_lane_ty = fx.clif_type(ret_lane_layout.ty).unwrap();
|
||||
|
||||
let from_signed = type_sign(lane_layout.ty);
|
||||
|
@ -33,22 +33,22 @@ pub fn codegen_simd_intrinsic_call<'tcx>(
|
|||
};
|
||||
|
||||
simd_eq, (c x, c y) {
|
||||
simd_cmp!(fx, intrinsic, Equal(x, y) -> ret);
|
||||
simd_cmp!(fx, Equal(x, y) -> ret);
|
||||
};
|
||||
simd_ne, (c x, c y) {
|
||||
simd_cmp!(fx, intrinsic, NotEqual(x, y) -> ret);
|
||||
simd_cmp!(fx, NotEqual(x, y) -> ret);
|
||||
};
|
||||
simd_lt, (c x, c y) {
|
||||
simd_cmp!(fx, intrinsic, UnsignedLessThan|SignedLessThan(x, y) -> ret);
|
||||
simd_cmp!(fx, UnsignedLessThan|SignedLessThan(x, y) -> ret);
|
||||
};
|
||||
simd_le, (c x, c y) {
|
||||
simd_cmp!(fx, intrinsic, UnsignedLessThanOrEqual|SignedLessThanOrEqual(x, y) -> ret);
|
||||
simd_cmp!(fx, UnsignedLessThanOrEqual|SignedLessThanOrEqual(x, y) -> ret);
|
||||
};
|
||||
simd_gt, (c x, c y) {
|
||||
simd_cmp!(fx, intrinsic, UnsignedGreaterThan|SignedGreaterThan(x, y) -> ret);
|
||||
simd_cmp!(fx, UnsignedGreaterThan|SignedGreaterThan(x, y) -> ret);
|
||||
};
|
||||
simd_ge, (c x, c y) {
|
||||
simd_cmp!(fx, intrinsic, UnsignedGreaterThanOrEqual|SignedGreaterThanOrEqual(x, y) -> ret);
|
||||
simd_cmp!(fx, UnsignedGreaterThanOrEqual|SignedGreaterThanOrEqual(x, y) -> ret);
|
||||
};
|
||||
|
||||
// simd_shuffle32<T, U>(x: T, y: T, idx: [u32; 32]) -> U
|
||||
|
|
|
@ -479,7 +479,7 @@ impl<'tcx> CPlace<'tcx> {
|
|||
CValueInner::ByVal(val) => {
|
||||
to_ptr.store(fx, val, MemFlags::new());
|
||||
}
|
||||
CValueInner::ByValPair(value, extra) => {
|
||||
CValueInner::ByValPair(_, _) => {
|
||||
bug!(
|
||||
"Non ScalarPair abi {:?} for ByValPair CValue",
|
||||
dst_layout.abi
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue