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rustc_target: RISC-V: add base "I"-related important extensions

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Of ratified RISC-V features defined, this commit adds extensions
satisfying following criteria:

*   Formerly a part of the "I" extension and splitted thereafter
    (now ratified as "I" + "Zifencei" + "Zicsr" + "Zicntr" + "Zihpm") or
*   Dicoverable from newer versions of the Linux kernel and implemented
    as a part of std_detect's feature ("Zihintpause").

This is based on the latest ratified ISA Manuals (version 20240411).

Additional (1):

One of those, "Zicsr", is a dependency of many other ISA extensions and
this commit adds correct dependencies to "Zicsr".

Additional (2):

In RISC-V, "G" is an abbreviation of following extensions:

*   "I"
*   "M"
*   "A"
*   "F"
*   "D"
*   "Zicsr" (although implied by "F")
*   "Zifencei"

and all RISC-V targets with the "G" abbreviation and targets for Android /
VxWorks are updated accordingly.

Note:

Android will require RVA22 (likely RVA22U64) and some more extensions,
which is a superset of RV64GC.  For VxWorks, all BSPs currently distributed
by Wind River are for boards with RV64GC (this commit also updates
riscv32-wrs-vxworks though).
This commit is contained in:
Tsukasa OI 2025-04-02 01:13:40 +00:00
parent 9b7d5ac818
commit 6f40f0cdab
16 changed files with 28 additions and 18 deletions
Download patch file Download diff file Expand all files Collapse all files

2
compiler/rustc_target/src/spec/targets/riscv32_wrs_vxworks.rs
View file

@ -16,7 +16,7 @@ pub(crate) fn target() -> Target {
cpu: "generic-rv32".into(),
llvm_abiname: "ilp32d".into(),
max_atomic_width: Some(32),
features: "+m,+a,+f,+d,+c".into(),
features: "+m,+a,+f,+d,+c,+zicsr,+zifencei".into(),
stack_probes: StackProbeType::Inline,
..base::vxworks::opts()
},

2
compiler/rustc_target/src/spec/targets/riscv32gc_unknown_linux_gnu.rs
View file

@ -17,7 +17,7 @@ pub(crate) fn target() -> Target {
options: TargetOptions {
code_model: Some(CodeModel::Medium),
cpu: "generic-rv32".into(),
features: "+m,+a,+f,+d,+c".into(),
features: "+m,+a,+f,+d,+c,+zicsr,+zifencei".into(),
llvm_abiname: "ilp32d".into(),
max_atomic_width: Some(32),
supported_split_debuginfo: Cow::Borrowed(&[SplitDebuginfo::Off]),

2
compiler/rustc_target/src/spec/targets/riscv32gc_unknown_linux_musl.rs
View file

@ -19,7 +19,7 @@ pub(crate) fn target() -> Target {
options: TargetOptions {
code_model: Some(CodeModel::Medium),
cpu: "generic-rv32".into(),
features: "+m,+a,+f,+d,+c".into(),
features: "+m,+a,+f,+d,+c,+zicsr,+zifencei".into(),
llvm_abiname: "ilp32d".into(),
max_atomic_width: Some(32),
supported_split_debuginfo: Cow::Borrowed(&[SplitDebuginfo::Off]),

2
compiler/rustc_target/src/spec/targets/riscv64_linux_android.rs
View file

@ -19,7 +19,7 @@ pub(crate) fn target() -> Target {
options: TargetOptions {
code_model: Some(CodeModel::Medium),
cpu: "generic-rv64".into(),
features: "+m,+a,+f,+d,+c,+zba,+zbb,+zbs,+v".into(),
features: "+m,+a,+f,+d,+c,+zicsr,+zifencei,+zba,+zbb,+zbs,+v".into(),
llvm_abiname: "lp64d".into(),
supported_sanitizers: SanitizerSet::ADDRESS,
max_atomic_width: Some(64),

2
compiler/rustc_target/src/spec/targets/riscv64_wrs_vxworks.rs
View file

@ -16,7 +16,7 @@ pub(crate) fn target() -> Target {
cpu: "generic-rv64".into(),
llvm_abiname: "lp64d".into(),
max_atomic_width: Some(64),
features: "+m,+a,+f,+d,+c".into(),
features: "+m,+a,+f,+d,+c,+zicsr,+zifencei".into(),
stack_probes: StackProbeType::Inline,
..base::vxworks::opts()
},

2
compiler/rustc_target/src/spec/targets/riscv64gc_unknown_freebsd.rs
View file

@ -15,7 +15,7 @@ pub(crate) fn target() -> Target {
options: TargetOptions {
code_model: Some(CodeModel::Medium),
cpu: "generic-rv64".into(),
features: "+m,+a,+f,+d,+c".into(),
features: "+m,+a,+f,+d,+c,+zicsr,+zifencei".into(),
llvm_abiname: "lp64d".into(),
max_atomic_width: Some(64),
..base::freebsd::opts()

2
compiler/rustc_target/src/spec/targets/riscv64gc_unknown_fuchsia.rs
View file

@ -4,7 +4,7 @@ pub(crate) fn target() -> Target {
let mut base = base::fuchsia::opts();
base.code_model = Some(CodeModel::Medium);
base.cpu = "generic-rv64".into();
base.features = "+m,+a,+f,+d,+c".into();
base.features = "+m,+a,+f,+d,+c,+zicsr,+zifencei".into();
base.llvm_abiname = "lp64d".into();
base.max_atomic_width = Some(64);
base.stack_probes = StackProbeType::Inline;

2
compiler/rustc_target/src/spec/targets/riscv64gc_unknown_hermit.rs
View file

@ -14,7 +14,7 @@ pub(crate) fn target() -> Target {
data_layout: "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128".into(),
options: TargetOptions {
cpu: "generic-rv64".into(),
features: "+m,+a,+f,+d,+c".into(),
features: "+m,+a,+f,+d,+c,+zicsr,+zifencei".into(),
relocation_model: RelocModel::Pic,
code_model: Some(CodeModel::Medium),
tls_model: TlsModel::LocalExec,

2
compiler/rustc_target/src/spec/targets/riscv64gc_unknown_linux_gnu.rs
View file

@ -17,7 +17,7 @@ pub(crate) fn target() -> Target {
options: TargetOptions {
code_model: Some(CodeModel::Medium),
cpu: "generic-rv64".into(),
features: "+m,+a,+f,+d,+c".into(),
features: "+m,+a,+f,+d,+c,+zicsr,+zifencei".into(),
llvm_abiname: "lp64d".into(),
max_atomic_width: Some(64),
supported_split_debuginfo: Cow::Borrowed(&[SplitDebuginfo::Off]),

2
compiler/rustc_target/src/spec/targets/riscv64gc_unknown_linux_musl.rs
View file

@ -17,7 +17,7 @@ pub(crate) fn target() -> Target {
options: TargetOptions {
code_model: Some(CodeModel::Medium),
cpu: "generic-rv64".into(),
features: "+m,+a,+f,+d,+c".into(),
features: "+m,+a,+f,+d,+c,+zicsr,+zifencei".into(),
llvm_abiname: "lp64d".into(),
max_atomic_width: Some(64),
supported_split_debuginfo: Cow::Borrowed(&[SplitDebuginfo::Off]),

2
compiler/rustc_target/src/spec/targets/riscv64gc_unknown_netbsd.rs
View file

@ -15,7 +15,7 @@ pub(crate) fn target() -> Target {
options: TargetOptions {
code_model: Some(CodeModel::Medium),
cpu: "generic-rv64".into(),
features: "+m,+a,+f,+d,+c".into(),
features: "+m,+a,+f,+d,+c,+zicsr,+zifencei".into(),
llvm_abiname: "lp64d".into(),
max_atomic_width: Some(64),
mcount: "__mcount".into(),

2
compiler/rustc_target/src/spec/targets/riscv64gc_unknown_none_elf.rs
View file

@ -22,7 +22,7 @@ pub(crate) fn target() -> Target {
llvm_abiname: "lp64d".into(),
cpu: "generic-rv64".into(),
max_atomic_width: Some(64),
features: "+m,+a,+f,+d,+c".into(),
features: "+m,+a,+f,+d,+c,+zicsr,+zifencei".into(),
panic_strategy: PanicStrategy::Abort,
relocation_model: RelocModel::Static,
code_model: Some(CodeModel::Medium),

2
compiler/rustc_target/src/spec/targets/riscv64gc_unknown_nuttx_elf.rs
View file

@ -24,7 +24,7 @@ pub(crate) fn target() -> Target {
llvm_abiname: "lp64d".into(),
cpu: "generic-rv64".into(),
max_atomic_width: Some(64),
features: "+m,+a,+f,+d,+c".into(),
features: "+m,+a,+f,+d,+c,+zicsr,+zifencei".into(),
panic_strategy: PanicStrategy::Abort,
relocation_model: RelocModel::Static,
code_model: Some(CodeModel::Medium),

2
compiler/rustc_target/src/spec/targets/riscv64gc_unknown_openbsd.rs
View file

@ -15,7 +15,7 @@ pub(crate) fn target() -> Target {
options: TargetOptions {
code_model: Some(CodeModel::Medium),
cpu: "generic-rv64".into(),
features: "+m,+a,+f,+d,+c".into(),
features: "+m,+a,+f,+d,+c,+zicsr,+zifencei".into(),
llvm_abiname: "lp64d".into(),
max_atomic_width: Some(64),
..base::openbsd::opts()

13
compiler/rustc_target/src/target_features.rs
View file

@ -488,7 +488,7 @@ static RISCV_FEATURES: &[(&str, Stability, ImpliedFeatures)] = &[
("c", Stable, &[]),
("d", Unstable(sym::riscv_target_feature), &["f"]),
("e", Unstable(sym::riscv_target_feature), &[]),
("f", Unstable(sym::riscv_target_feature), &[]),
("f", Unstable(sym::riscv_target_feature), &["zicsr"]),
(
"forced-atomics",
Stability::Forbidden { reason: "unsound because it changes the ABI of atomic operations" },
@ -517,15 +517,20 @@ static RISCV_FEATURES: &[(&str, Stability, ImpliedFeatures)] = &[
("zdinx", Unstable(sym::riscv_target_feature), &["zfinx"]),
("zfh", Unstable(sym::riscv_target_feature), &["zfhmin"]),
("zfhmin", Unstable(sym::riscv_target_feature), &["f"]),
("zfinx", Unstable(sym::riscv_target_feature), &[]),
("zfinx", Unstable(sym::riscv_target_feature), &["zicsr"]),
("zhinx", Unstable(sym::riscv_target_feature), &["zhinxmin"]),
("zhinxmin", Unstable(sym::riscv_target_feature), &["zfinx"]),
("zicntr", Unstable(sym::riscv_target_feature), &["zicsr"]),
("zicsr", Unstable(sym::riscv_target_feature), &[]),
("zifencei", Unstable(sym::riscv_target_feature), &[]),
("zihintpause", Unstable(sym::riscv_target_feature), &[]),
("zihpm", Unstable(sym::riscv_target_feature), &["zicsr"]),
("zk", Stable, &["zkn", "zkr", "zkt"]),
("zkn", Stable, &["zbkb", "zbkc", "zbkx", "zkne", "zknd", "zknh"]),
("zknd", Stable, &[]),
("zkne", Stable, &[]),
("zknh", Stable, &[]),
("zkr", Stable, &[]),
("zkr", Stable, &["zicsr"]),
("zks", Stable, &["zbkb", "zbkc", "zbkx", "zksed", "zksh"]),
("zksed", Stable, &[]),
("zksh", Stable, &[]),
@ -533,7 +538,7 @@ static RISCV_FEATURES: &[(&str, Stability, ImpliedFeatures)] = &[
("zvbb", Unstable(sym::riscv_target_feature), &["zvkb"]),
("zvbc", Unstable(sym::riscv_target_feature), &["zve64x"]),
("zve32f", Unstable(sym::riscv_target_feature), &["zve32x", "f"]),
("zve32x", Unstable(sym::riscv_target_feature), &["zvl32b"]),
("zve32x", Unstable(sym::riscv_target_feature), &["zvl32b", "zicsr"]),
("zve64d", Unstable(sym::riscv_target_feature), &["zve64f", "d"]),
("zve64f", Unstable(sym::riscv_target_feature), &["zve32f", "zve64x"]),
("zve64x", Unstable(sym::riscv_target_feature), &["zve32x", "zvl64b"]),