Rollup merge of #110482 - chrisnc:armv8r-target, r=wesleywiser
Add armv8r-none-eabihf target for the Cortex-R52.
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commit
6931780f40
8 changed files with 83 additions and 0 deletions
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@ -1543,6 +1543,7 @@ supported_targets! {
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("armebv7r-none-eabihf", armebv7r_none_eabihf),
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("armv7r-none-eabi", armv7r_none_eabi),
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("armv7r-none-eabihf", armv7r_none_eabihf),
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("armv8r-none-eabihf", armv8r_none_eabihf),
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("x86_64-pc-solaris", x86_64_pc_solaris),
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("sparcv9-sun-solaris", sparcv9_sun_solaris),
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35
compiler/rustc_target/src/spec/targets/armv8r_none_eabihf.rs
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35
compiler/rustc_target/src/spec/targets/armv8r_none_eabihf.rs
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@ -0,0 +1,35 @@
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// Targets the Little-endian Cortex-R52 processor (ARMv8-R)
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use crate::spec::{Cc, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetOptions};
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pub fn target() -> Target {
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Target {
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llvm_target: "armv8r-none-eabihf".into(),
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pointer_width: 32,
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data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
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arch: "arm".into(),
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options: TargetOptions {
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abi: "eabihf".into(),
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linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
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linker: Some("rust-lld".into()),
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relocation_model: RelocModel::Static,
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panic_strategy: PanicStrategy::Abort,
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// The Cortex-R52 has two variants with respect to floating-point support:
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// 1. fp-armv8, SP-only, with 16 DP (32 SP) registers
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// 2. neon-fp-armv8, SP+DP, with 32 DP registers
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// Use the lesser of these two options as the default, as it will produce code
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// compatible with either variant.
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//
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// Reference:
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// Arm Cortex-R52 Processor Technical Reference Manual
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// - Chapter 15 Advanced SIMD and floating-point support
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features: "+fp-armv8,-fp64,-d32".into(),
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max_atomic_width: Some(64),
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emit_debug_gdb_scripts: false,
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// GCC defaults to 8 for arm-none here.
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c_enum_min_bits: Some(8),
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..Default::default()
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},
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}
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}
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