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Auto merge of #52787 - riscv-rust:riscv-rust-pr, r=alexcrichton

Enable RISCV

- Enable LLVM backend.
- Implement call abi.
- Add built-in target riscv32imac-unknown-none.
- Enable CI.
This commit is contained in:
bors 2018-08-02 02:24:15 +00:00
commit 60c1ee7645
11 changed files with 139 additions and 4 deletions

View file

@ -171,6 +171,12 @@ bool LLVMRustPassManagerBuilderPopulateThinLTOPassManager(
#define SUBTARGET_MSP430
#endif
#ifdef LLVM_COMPONENT_RISCV
#define SUBTARGET_RISCV SUBTARGET(RISCV)
#else
#define SUBTARGET_RISCV
#endif
#ifdef LLVM_COMPONENT_SPARC
#define SUBTARGET_SPARC SUBTARGET(Sparc)
#else
@ -192,7 +198,8 @@ bool LLVMRustPassManagerBuilderPopulateThinLTOPassManager(
SUBTARGET_SYSTEMZ \
SUBTARGET_MSP430 \
SUBTARGET_SPARC \
SUBTARGET_HEXAGON
SUBTARGET_HEXAGON \
SUBTARGET_RISCV \
#define SUBTARGET(x) \
namespace llvm { \