Add support for const operands and options to global_asm!
On x86, the default syntax is also switched to Intel to match asm!
This commit is contained in:
Amanieu d'Antras
parent
952c5732c2
commit
5918ee4317
36 changed files with 928 additions and 800 deletions
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@ -3,7 +3,6 @@ use super::{ImplTraitContext, LoweringContext, ParamMode, ParenthesizedGenericAr
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use rustc_ast::attr;
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use rustc_ast::ptr::P as AstP;
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use rustc_ast::*;
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use rustc_data_structures::fx::FxHashMap;
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use rustc_data_structures::stack::ensure_sufficient_stack;
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use rustc_data_structures::thin_vec::ThinVec;
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use rustc_errors::struct_span_err;
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@ -15,9 +14,6 @@ use rustc_span::hygiene::ExpnId;
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use rustc_span::source_map::{respan, DesugaringKind, Span, Spanned};
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use rustc_span::symbol::{sym, Ident, Symbol};
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use rustc_span::{hygiene::ForLoopLoc, DUMMY_SP};
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use rustc_target::asm;
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use std::collections::hash_map::Entry;
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use std::fmt::Write;
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impl<'hir> LoweringContext<'_, 'hir> {
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fn lower_exprs(&mut self, exprs: &[AstP<Expr>]) -> &'hir [hir::Expr<'hir>] {
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@ -222,7 +218,9 @@ impl<'hir> LoweringContext<'_, 'hir> {
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let e = e.as_ref().map(|x| self.lower_expr(x));
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hir::ExprKind::Ret(e)
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}
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ExprKind::InlineAsm(ref asm) => self.lower_expr_asm(e.span, asm),
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ExprKind::InlineAsm(ref asm) => {
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hir::ExprKind::InlineAsm(self.lower_inline_asm(e.span, asm))
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}
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ExprKind::LlvmInlineAsm(ref asm) => self.lower_expr_llvm_asm(asm),
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ExprKind::Struct(ref se) => {
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let rest = match &se.rest {
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@ -1329,319 +1327,6 @@ impl<'hir> LoweringContext<'_, 'hir> {
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result
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}
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fn lower_expr_asm(&mut self, sp: Span, asm: &InlineAsm) -> hir::ExprKind<'hir> {
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// Rustdoc needs to support asm! from foriegn architectures: don't try
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// lowering the register contraints in this case.
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let asm_arch = if self.sess.opts.actually_rustdoc { None } else { self.sess.asm_arch };
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if asm_arch.is_none() && !self.sess.opts.actually_rustdoc {
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struct_span_err!(self.sess, sp, E0472, "asm! is unsupported on this target").emit();
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}
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if asm.options.contains(InlineAsmOptions::ATT_SYNTAX)
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&& !matches!(asm_arch, Some(asm::InlineAsmArch::X86 | asm::InlineAsmArch::X86_64))
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&& !self.sess.opts.actually_rustdoc
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{
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self.sess
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.struct_span_err(sp, "the `att_syntax` option is only supported on x86")
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.emit();
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}
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// Lower operands to HIR. We use dummy register classes if an error
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// occurs during lowering because we still need to be able to produce a
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// valid HIR.
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let sess = self.sess;
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let operands: Vec<_> = asm
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.operands
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.iter()
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.map(|(op, op_sp)| {
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let lower_reg = |reg| match reg {
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InlineAsmRegOrRegClass::Reg(s) => {
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asm::InlineAsmRegOrRegClass::Reg(if let Some(asm_arch) = asm_arch {
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asm::InlineAsmReg::parse(
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asm_arch,
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|feature| sess.target_features.contains(&Symbol::intern(feature)),
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&sess.target,
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s,
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)
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.unwrap_or_else(|e| {
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let msg = format!("invalid register `{}`: {}", s.as_str(), e);
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sess.struct_span_err(*op_sp, &msg).emit();
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asm::InlineAsmReg::Err
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})
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} else {
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asm::InlineAsmReg::Err
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})
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}
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InlineAsmRegOrRegClass::RegClass(s) => {
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asm::InlineAsmRegOrRegClass::RegClass(if let Some(asm_arch) = asm_arch {
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asm::InlineAsmRegClass::parse(asm_arch, s).unwrap_or_else(|e| {
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let msg = format!("invalid register class `{}`: {}", s.as_str(), e);
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sess.struct_span_err(*op_sp, &msg).emit();
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asm::InlineAsmRegClass::Err
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})
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} else {
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asm::InlineAsmRegClass::Err
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})
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}
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};
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let op = match *op {
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InlineAsmOperand::In { reg, ref expr } => hir::InlineAsmOperand::In {
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reg: lower_reg(reg),
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expr: self.lower_expr_mut(expr),
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},
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InlineAsmOperand::Out { reg, late, ref expr } => hir::InlineAsmOperand::Out {
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reg: lower_reg(reg),
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late,
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expr: expr.as_ref().map(|expr| self.lower_expr_mut(expr)),
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},
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InlineAsmOperand::InOut { reg, late, ref expr } => {
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hir::InlineAsmOperand::InOut {
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reg: lower_reg(reg),
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late,
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expr: self.lower_expr_mut(expr),
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}
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}
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InlineAsmOperand::SplitInOut { reg, late, ref in_expr, ref out_expr } => {
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hir::InlineAsmOperand::SplitInOut {
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reg: lower_reg(reg),
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late,
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in_expr: self.lower_expr_mut(in_expr),
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out_expr: out_expr.as_ref().map(|expr| self.lower_expr_mut(expr)),
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}
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}
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InlineAsmOperand::Const { ref anon_const } => hir::InlineAsmOperand::Const {
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anon_const: self.lower_anon_const(anon_const),
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},
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InlineAsmOperand::Sym { ref expr } => {
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hir::InlineAsmOperand::Sym { expr: self.lower_expr_mut(expr) }
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}
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};
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(op, *op_sp)
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})
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.collect();
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// Validate template modifiers against the register classes for the operands
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for p in &asm.template {
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if let InlineAsmTemplatePiece::Placeholder {
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operand_idx,
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modifier: Some(modifier),
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span: placeholder_span,
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} = *p
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{
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let op_sp = asm.operands[operand_idx].1;
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match &operands[operand_idx].0 {
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hir::InlineAsmOperand::In { reg, .. }
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| hir::InlineAsmOperand::Out { reg, .. }
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| hir::InlineAsmOperand::InOut { reg, .. }
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| hir::InlineAsmOperand::SplitInOut { reg, .. } => {
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let class = reg.reg_class();
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if class == asm::InlineAsmRegClass::Err {
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continue;
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}
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let valid_modifiers = class.valid_modifiers(asm_arch.unwrap());
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if !valid_modifiers.contains(&modifier) {
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let mut err = sess.struct_span_err(
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placeholder_span,
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"invalid asm template modifier for this register class",
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);
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err.span_label(placeholder_span, "template modifier");
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err.span_label(op_sp, "argument");
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if !valid_modifiers.is_empty() {
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let mut mods = format!("`{}`", valid_modifiers[0]);
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for m in &valid_modifiers[1..] {
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let _ = write!(mods, ", `{}`", m);
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}
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err.note(&format!(
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"the `{}` register class supports \
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the following template modifiers: {}",
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class.name(),
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mods
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));
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} else {
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err.note(&format!(
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"the `{}` register class does not support template modifiers",
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class.name()
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));
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}
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err.emit();
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}
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}
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hir::InlineAsmOperand::Const { .. } => {
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let mut err = sess.struct_span_err(
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placeholder_span,
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"asm template modifiers are not allowed for `const` arguments",
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);
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err.span_label(placeholder_span, "template modifier");
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err.span_label(op_sp, "argument");
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err.emit();
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}
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hir::InlineAsmOperand::Sym { .. } => {
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let mut err = sess.struct_span_err(
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placeholder_span,
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"asm template modifiers are not allowed for `sym` arguments",
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);
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err.span_label(placeholder_span, "template modifier");
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err.span_label(op_sp, "argument");
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err.emit();
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}
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}
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}
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}
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let mut used_input_regs = FxHashMap::default();
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let mut used_output_regs = FxHashMap::default();
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let mut required_features: Vec<&str> = vec![];
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for (idx, &(ref op, op_sp)) in operands.iter().enumerate() {
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if let Some(reg) = op.reg() {
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// Make sure we don't accidentally carry features from the
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// previous iteration.
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required_features.clear();
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let reg_class = reg.reg_class();
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if reg_class == asm::InlineAsmRegClass::Err {
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continue;
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}
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// We ignore target feature requirements for clobbers: if the
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// feature is disabled then the compiler doesn't care what we
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// do with the registers.
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//
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// Note that this is only possible for explicit register
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// operands, which cannot be used in the asm string.
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let is_clobber = matches!(
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op,
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hir::InlineAsmOperand::Out {
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reg: asm::InlineAsmRegOrRegClass::Reg(_),
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late: _,
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expr: None
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}
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);
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if !is_clobber {
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// Validate register classes against currently enabled target
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// features. We check that at least one type is available for
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// the current target.
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for &(_, feature) in reg_class.supported_types(asm_arch.unwrap()) {
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if let Some(feature) = feature {
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if self.sess.target_features.contains(&Symbol::intern(feature)) {
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required_features.clear();
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break;
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} else {
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required_features.push(feature);
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}
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} else {
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required_features.clear();
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break;
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}
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}
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// We are sorting primitive strs here and can use unstable sort here
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required_features.sort_unstable();
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required_features.dedup();
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match &required_features[..] {
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[] => {}
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[feature] => {
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let msg = format!(
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"register class `{}` requires the `{}` target feature",
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reg_class.name(),
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feature
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);
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sess.struct_span_err(op_sp, &msg).emit();
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}
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features => {
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let msg = format!(
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"register class `{}` requires at least one target feature: {}",
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reg_class.name(),
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features.join(", ")
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);
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sess.struct_span_err(op_sp, &msg).emit();
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}
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}
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}
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// Check for conflicts between explicit register operands.
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if let asm::InlineAsmRegOrRegClass::Reg(reg) = reg {
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let (input, output) = match op {
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hir::InlineAsmOperand::In { .. } => (true, false),
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// Late output do not conflict with inputs, but normal outputs do
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hir::InlineAsmOperand::Out { late, .. } => (!late, true),
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hir::InlineAsmOperand::InOut { .. }
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| hir::InlineAsmOperand::SplitInOut { .. } => (true, true),
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hir::InlineAsmOperand::Const { .. } | hir::InlineAsmOperand::Sym { .. } => {
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unreachable!()
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}
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};
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// Flag to output the error only once per operand
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let mut skip = false;
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reg.overlapping_regs(|r| {
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let mut check = |used_regs: &mut FxHashMap<asm::InlineAsmReg, usize>,
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input| {
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match used_regs.entry(r) {
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Entry::Occupied(o) => {
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if skip {
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return;
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}
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skip = true;
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let idx2 = *o.get();
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let &(ref op2, op_sp2) = &operands[idx2];
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let reg2 = match op2.reg() {
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Some(asm::InlineAsmRegOrRegClass::Reg(r)) => r,
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_ => unreachable!(),
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};
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let msg = format!(
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"register `{}` conflicts with register `{}`",
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reg.name(),
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reg2.name()
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);
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let mut err = sess.struct_span_err(op_sp, &msg);
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err.span_label(op_sp, &format!("register `{}`", reg.name()));
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err.span_label(op_sp2, &format!("register `{}`", reg2.name()));
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match (op, op2) {
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(
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hir::InlineAsmOperand::In { .. },
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hir::InlineAsmOperand::Out { late, .. },
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)
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| (
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hir::InlineAsmOperand::Out { late, .. },
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hir::InlineAsmOperand::In { .. },
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) => {
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assert!(!*late);
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let out_op_sp = if input { op_sp2 } else { op_sp };
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let msg = "use `lateout` instead of \
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`out` to avoid conflict";
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err.span_help(out_op_sp, msg);
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}
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_ => {}
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}
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err.emit();
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}
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Entry::Vacant(v) => {
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v.insert(idx);
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}
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}
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};
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if input {
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check(&mut used_input_regs, true);
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}
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if output {
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check(&mut used_output_regs, false);
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}
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});
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}
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}
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}
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let operands = self.arena.alloc_from_iter(operands);
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let template = self.arena.alloc_from_iter(asm.template.iter().cloned());
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let line_spans = self.arena.alloc_slice(&asm.line_spans[..]);
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let hir_asm = hir::InlineAsm { template, operands, options: asm.options, line_spans };
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hir::ExprKind::InlineAsm(self.arena.alloc(hir_asm))
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}
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fn lower_expr_llvm_asm(&mut self, asm: &LlvmInlineAsm) -> hir::ExprKind<'hir> {
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let inner = hir::LlvmInlineAsmInner {
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inputs: asm.inputs.iter().map(|&(c, _)| c).collect(),
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