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Rollup merge of #112168 - scottmcm:lower-div-rem-unchecked-to-mir, r=oli-obk

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Lower `unchecked_div`/`_rem` to MIR's `BinOp::Div`/`Rem`

As described in <https://doc.rust-lang.org/nightly/nightly-rustc/rustc_middle/mir/enum.BinOp.html#variant.Div>, the ordinary `BinOp`s for these are already UB for division by zero ([or overflow](https://llvm.org/docs/LangRef.html#sdiv-instruction), [demo](https://rust.godbolt.org/z/71e7P7Exh)), as MIR building is responsible for inserting code to panic for those cases regardless of whether the overflow checks are enabled.

So we can lower these in the same arm that lowers `wrapping_add` to MIR `BinOp::Add` and such, as all these cases turn into ordinary `Rvalue::BinaryOp`s.
This commit is contained in:
Michael Goulet 2023-06-02 16:02:06 -07:00 • committed by GitHub
commit 5460f92a0f
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27 changed files with 134 additions and 81 deletions
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5
compiler/rustc_codegen_cranelift/src/intrinsics/mod.rs
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@ -475,9 +475,7 @@ fn codegen_regular_intrinsic_call<'tcx>(
sym::unchecked_add
| sym::unchecked_sub
| sym::unchecked_mul
| sym::unchecked_div
| sym::exact_div
| sym::unchecked_rem
| sym::unchecked_shl
| sym::unchecked_shr => {
intrinsic_args!(fx, args => (x, y); intrinsic);
@ -487,8 +485,7 @@ fn codegen_regular_intrinsic_call<'tcx>(
sym::unchecked_add => BinOp::Add,
sym::unchecked_sub => BinOp::Sub,
sym::unchecked_mul => BinOp::Mul,
sym::unchecked_div | sym::exact_div => BinOp::Div,
sym::unchecked_rem => BinOp::Rem,
sym::exact_div => BinOp::Div,
sym::unchecked_shl => BinOp::Shl,
sym::unchecked_shr => BinOp::Shr,
_ => unreachable!(),