Merge commit '1bbee3e217' into sync-cg_gcc-2023-06-19
This commit is contained in:
Antoni Boucher
commit
4d96893d85
23 changed files with 244 additions and 264 deletions
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@ -2967,10 +2967,6 @@ match name {
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"llvm.nvvm.clz.ll" => "__nvvm_clz_ll",
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"llvm.nvvm.cos.approx.f" => "__nvvm_cos_approx_f",
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"llvm.nvvm.cos.approx.ftz.f" => "__nvvm_cos_approx_ftz_f",
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"llvm.nvvm.cp.async.ca.shared.global.16" => "__nvvm_cp_async_ca_shared_global_16",
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"llvm.nvvm.cp.async.ca.shared.global.4" => "__nvvm_cp_async_ca_shared_global_4",
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"llvm.nvvm.cp.async.ca.shared.global.8" => "__nvvm_cp_async_ca_shared_global_8",
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"llvm.nvvm.cp.async.cg.shared.global.16" => "__nvvm_cp_async_cg_shared_global_16",
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"llvm.nvvm.cp.async.commit.group" => "__nvvm_cp_async_commit_group",
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"llvm.nvvm.cp.async.mbarrier.arrive" => "__nvvm_cp_async_mbarrier_arrive",
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"llvm.nvvm.cp.async.mbarrier.arrive.noinc" => "__nvvm_cp_async_mbarrier_arrive_noinc",
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@ -3086,18 +3082,8 @@ match name {
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"llvm.nvvm.fma.rn.f16" => "__nvvm_fma_rn_f16",
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"llvm.nvvm.fma.rn.f16x2" => "__nvvm_fma_rn_f16x2",
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"llvm.nvvm.fma.rn.ftz.f" => "__nvvm_fma_rn_ftz_f",
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"llvm.nvvm.fma.rn.ftz.f16" => "__nvvm_fma_rn_ftz_f16",
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"llvm.nvvm.fma.rn.ftz.f16x2" => "__nvvm_fma_rn_ftz_f16x2",
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"llvm.nvvm.fma.rn.ftz.relu.f16" => "__nvvm_fma_rn_ftz_relu_f16",
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"llvm.nvvm.fma.rn.ftz.relu.f16x2" => "__nvvm_fma_rn_ftz_relu_f16x2",
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"llvm.nvvm.fma.rn.ftz.sat.f16" => "__nvvm_fma_rn_ftz_sat_f16",
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"llvm.nvvm.fma.rn.ftz.sat.f16x2" => "__nvvm_fma_rn_ftz_sat_f16x2",
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"llvm.nvvm.fma.rn.relu.bf16" => "__nvvm_fma_rn_relu_bf16",
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"llvm.nvvm.fma.rn.relu.bf16x2" => "__nvvm_fma_rn_relu_bf16x2",
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"llvm.nvvm.fma.rn.relu.f16" => "__nvvm_fma_rn_relu_f16",
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"llvm.nvvm.fma.rn.relu.f16x2" => "__nvvm_fma_rn_relu_f16x2",
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"llvm.nvvm.fma.rn.sat.f16" => "__nvvm_fma_rn_sat_f16",
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"llvm.nvvm.fma.rn.sat.f16x2" => "__nvvm_fma_rn_sat_f16x2",
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"llvm.nvvm.fma.rp.d" => "__nvvm_fma_rp_d",
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"llvm.nvvm.fma.rp.f" => "__nvvm_fma_rp_f",
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"llvm.nvvm.fma.rp.ftz.f" => "__nvvm_fma_rp_ftz_f",
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@ -3111,32 +3097,18 @@ match name {
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"llvm.nvvm.fmax.f16" => "__nvvm_fmax_f16",
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"llvm.nvvm.fmax.f16x2" => "__nvvm_fmax_f16x2",
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"llvm.nvvm.fmax.ftz.f" => "__nvvm_fmax_ftz_f",
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"llvm.nvvm.fmax.ftz.f16" => "__nvvm_fmax_ftz_f16",
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"llvm.nvvm.fmax.ftz.f16x2" => "__nvvm_fmax_ftz_f16x2",
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"llvm.nvvm.fmax.ftz.nan.f" => "__nvvm_fmax_ftz_nan_f",
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"llvm.nvvm.fmax.ftz.nan.f16" => "__nvvm_fmax_ftz_nan_f16",
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"llvm.nvvm.fmax.ftz.nan.f16x2" => "__nvvm_fmax_ftz_nan_f16x2",
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"llvm.nvvm.fmax.ftz.nan.xorsign.abs.f" => "__nvvm_fmax_ftz_nan_xorsign_abs_f",
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"llvm.nvvm.fmax.ftz.nan.xorsign.abs.f16" => "__nvvm_fmax_ftz_nan_xorsign_abs_f16",
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"llvm.nvvm.fmax.ftz.nan.xorsign.abs.f16x2" => "__nvvm_fmax_ftz_nan_xorsign_abs_f16x2",
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"llvm.nvvm.fmax.ftz.xorsign.abs.f" => "__nvvm_fmax_ftz_xorsign_abs_f",
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"llvm.nvvm.fmax.ftz.xorsign.abs.f16" => "__nvvm_fmax_ftz_xorsign_abs_f16",
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"llvm.nvvm.fmax.ftz.xorsign.abs.f16x2" => "__nvvm_fmax_ftz_xorsign_abs_f16x2",
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"llvm.nvvm.fmax.nan.bf16" => "__nvvm_fmax_nan_bf16",
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"llvm.nvvm.fmax.nan.bf16x2" => "__nvvm_fmax_nan_bf16x2",
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"llvm.nvvm.fmax.nan.f" => "__nvvm_fmax_nan_f",
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"llvm.nvvm.fmax.nan.f16" => "__nvvm_fmax_nan_f16",
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"llvm.nvvm.fmax.nan.f16x2" => "__nvvm_fmax_nan_f16x2",
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"llvm.nvvm.fmax.nan.xorsign.abs.bf16" => "__nvvm_fmax_nan_xorsign_abs_bf16",
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"llvm.nvvm.fmax.nan.xorsign.abs.bf16x2" => "__nvvm_fmax_nan_xorsign_abs_bf16x2",
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"llvm.nvvm.fmax.nan.xorsign.abs.f" => "__nvvm_fmax_nan_xorsign_abs_f",
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"llvm.nvvm.fmax.nan.xorsign.abs.f16" => "__nvvm_fmax_nan_xorsign_abs_f16",
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"llvm.nvvm.fmax.nan.xorsign.abs.f16x2" => "__nvvm_fmax_nan_xorsign_abs_f16x2",
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"llvm.nvvm.fmax.xorsign.abs.bf16" => "__nvvm_fmax_xorsign_abs_bf16",
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"llvm.nvvm.fmax.xorsign.abs.bf16x2" => "__nvvm_fmax_xorsign_abs_bf16x2",
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"llvm.nvvm.fmax.xorsign.abs.f" => "__nvvm_fmax_xorsign_abs_f",
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"llvm.nvvm.fmax.xorsign.abs.f16" => "__nvvm_fmax_xorsign_abs_f16",
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"llvm.nvvm.fmax.xorsign.abs.f16x2" => "__nvvm_fmax_xorsign_abs_f16x2",
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"llvm.nvvm.fmin.bf16" => "__nvvm_fmin_bf16",
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"llvm.nvvm.fmin.bf16x2" => "__nvvm_fmin_bf16x2",
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"llvm.nvvm.fmin.d" => "__nvvm_fmin_d",
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@ -3144,32 +3116,18 @@ match name {
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"llvm.nvvm.fmin.f16" => "__nvvm_fmin_f16",
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"llvm.nvvm.fmin.f16x2" => "__nvvm_fmin_f16x2",
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"llvm.nvvm.fmin.ftz.f" => "__nvvm_fmin_ftz_f",
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"llvm.nvvm.fmin.ftz.f16" => "__nvvm_fmin_ftz_f16",
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"llvm.nvvm.fmin.ftz.f16x2" => "__nvvm_fmin_ftz_f16x2",
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"llvm.nvvm.fmin.ftz.nan.f" => "__nvvm_fmin_ftz_nan_f",
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"llvm.nvvm.fmin.ftz.nan.f16" => "__nvvm_fmin_ftz_nan_f16",
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"llvm.nvvm.fmin.ftz.nan.f16x2" => "__nvvm_fmin_ftz_nan_f16x2",
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"llvm.nvvm.fmin.ftz.nan.xorsign.abs.f" => "__nvvm_fmin_ftz_nan_xorsign_abs_f",
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"llvm.nvvm.fmin.ftz.nan.xorsign.abs.f16" => "__nvvm_fmin_ftz_nan_xorsign_abs_f16",
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"llvm.nvvm.fmin.ftz.nan.xorsign.abs.f16x2" => "__nvvm_fmin_ftz_nan_xorsign_abs_f16x2",
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"llvm.nvvm.fmin.ftz.xorsign.abs.f" => "__nvvm_fmin_ftz_xorsign_abs_f",
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"llvm.nvvm.fmin.ftz.xorsign.abs.f16" => "__nvvm_fmin_ftz_xorsign_abs_f16",
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"llvm.nvvm.fmin.ftz.xorsign.abs.f16x2" => "__nvvm_fmin_ftz_xorsign_abs_f16x2",
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"llvm.nvvm.fmin.nan.bf16" => "__nvvm_fmin_nan_bf16",
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"llvm.nvvm.fmin.nan.bf16x2" => "__nvvm_fmin_nan_bf16x2",
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"llvm.nvvm.fmin.nan.f" => "__nvvm_fmin_nan_f",
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"llvm.nvvm.fmin.nan.f16" => "__nvvm_fmin_nan_f16",
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"llvm.nvvm.fmin.nan.f16x2" => "__nvvm_fmin_nan_f16x2",
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"llvm.nvvm.fmin.nan.xorsign.abs.bf16" => "__nvvm_fmin_nan_xorsign_abs_bf16",
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"llvm.nvvm.fmin.nan.xorsign.abs.bf16x2" => "__nvvm_fmin_nan_xorsign_abs_bf16x2",
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"llvm.nvvm.fmin.nan.xorsign.abs.f" => "__nvvm_fmin_nan_xorsign_abs_f",
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"llvm.nvvm.fmin.nan.xorsign.abs.f16" => "__nvvm_fmin_nan_xorsign_abs_f16",
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"llvm.nvvm.fmin.nan.xorsign.abs.f16x2" => "__nvvm_fmin_nan_xorsign_abs_f16x2",
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"llvm.nvvm.fmin.xorsign.abs.bf16" => "__nvvm_fmin_xorsign_abs_bf16",
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"llvm.nvvm.fmin.xorsign.abs.bf16x2" => "__nvvm_fmin_xorsign_abs_bf16x2",
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"llvm.nvvm.fmin.xorsign.abs.f" => "__nvvm_fmin_xorsign_abs_f",
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"llvm.nvvm.fmin.xorsign.abs.f16" => "__nvvm_fmin_xorsign_abs_f16",
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"llvm.nvvm.fmin.xorsign.abs.f16x2" => "__nvvm_fmin_xorsign_abs_f16x2",
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"llvm.nvvm.fns" => "__nvvm_fns",
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"llvm.nvvm.h2f" => "__nvvm_h2f",
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"llvm.nvvm.i2d.rm" => "__nvvm_i2d_rm",
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@ -7895,6 +7853,10 @@ match name {
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"llvm.x86.subborrow.u64" => "__builtin_ia32_subborrow_u64",
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"llvm.x86.tbm.bextri.u32" => "__builtin_ia32_bextri_u32",
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"llvm.x86.tbm.bextri.u64" => "__builtin_ia32_bextri_u64",
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"llvm.x86.tcmmimfp16ps" => "__builtin_ia32_tcmmimfp16ps",
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"llvm.x86.tcmmimfp16ps.internal" => "__builtin_ia32_tcmmimfp16ps_internal",
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"llvm.x86.tcmmrlfp16ps" => "__builtin_ia32_tcmmrlfp16ps",
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"llvm.x86.tcmmrlfp16ps.internal" => "__builtin_ia32_tcmmrlfp16ps_internal",
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"llvm.x86.tdpbf16ps" => "__builtin_ia32_tdpbf16ps",
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"llvm.x86.tdpbf16ps.internal" => "__builtin_ia32_tdpbf16ps_internal",
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"llvm.x86.tdpbssd" => "__builtin_ia32_tdpbssd",
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@ -313,6 +313,13 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc
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let new_args = args.to_vec();
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args = vec![new_args[1], new_args[0], new_args[2], new_args[3], new_args[4]].into();
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},
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"__builtin_ia32_vpshrdv_v8di" | "__builtin_ia32_vpshrdv_v4di" | "__builtin_ia32_vpshrdv_v2di" |
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"__builtin_ia32_vpshrdv_v16si" | "__builtin_ia32_vpshrdv_v8si" | "__builtin_ia32_vpshrdv_v4si" |
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"__builtin_ia32_vpshrdv_v32hi" | "__builtin_ia32_vpshrdv_v16hi" | "__builtin_ia32_vpshrdv_v8hi" => {
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// The first two arguments are reversed, compared to LLVM.
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let new_args = args.to_vec();
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args = vec![new_args[1], new_args[0], new_args[2]].into();
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},
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_ => (),
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}
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}
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@ -551,141 +551,52 @@ impl<'a, 'gcc, 'tcx> Builder<'a, 'gcc, 'tcx> {
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let context = &self.cx.context;
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let result =
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match width {
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8 => {
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8 | 16 | 32 | 64 => {
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let mask = ((1u128 << width) - 1) as u64;
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let (m0, m1, m2) = if width > 16 {
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(
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context.new_rvalue_from_long(typ, (0x5555555555555555u64 & mask) as i64),
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context.new_rvalue_from_long(typ, (0x3333333333333333u64 & mask) as i64),
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context.new_rvalue_from_long(typ, (0x0f0f0f0f0f0f0f0fu64 & mask) as i64),
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)
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} else {
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(
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context.new_rvalue_from_int(typ, (0x5555u64 & mask) as i32),
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context.new_rvalue_from_int(typ, (0x3333u64 & mask) as i32),
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context.new_rvalue_from_int(typ, (0x0f0fu64 & mask) as i32),
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)
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};
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let one = context.new_rvalue_from_int(typ, 1);
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let two = context.new_rvalue_from_int(typ, 2);
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let four = context.new_rvalue_from_int(typ, 4);
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// First step.
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let left = self.and(value, context.new_rvalue_from_int(typ, 0xF0));
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let left = self.lshr(left, context.new_rvalue_from_int(typ, 4));
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let right = self.and(value, context.new_rvalue_from_int(typ, 0x0F));
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let right = self.shl(right, context.new_rvalue_from_int(typ, 4));
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let left = self.lshr(value, one);
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let left = self.and(left, m0);
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let right = self.and(value, m0);
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let right = self.shl(right, one);
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let step1 = self.or(left, right);
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// Second step.
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let left = self.and(step1, context.new_rvalue_from_int(typ, 0xCC));
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let left = self.lshr(left, context.new_rvalue_from_int(typ, 2));
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let right = self.and(step1, context.new_rvalue_from_int(typ, 0x33));
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let right = self.shl(right, context.new_rvalue_from_int(typ, 2));
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let left = self.lshr(step1, two);
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let left = self.and(left, m1);
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let right = self.and(step1, m1);
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let right = self.shl(right, two);
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let step2 = self.or(left, right);
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// Third step.
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let left = self.and(step2, context.new_rvalue_from_int(typ, 0xAA));
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let left = self.lshr(left, context.new_rvalue_from_int(typ, 1));
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let right = self.and(step2, context.new_rvalue_from_int(typ, 0x55));
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let right = self.shl(right, context.new_rvalue_from_int(typ, 1));
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let step3 = self.or(left, right);
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step3
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},
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16 => {
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// First step.
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let left = self.and(value, context.new_rvalue_from_int(typ, 0x5555));
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let left = self.shl(left, context.new_rvalue_from_int(typ, 1));
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let right = self.and(value, context.new_rvalue_from_int(typ, 0xAAAA));
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let right = self.lshr(right, context.new_rvalue_from_int(typ, 1));
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let step1 = self.or(left, right);
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// Second step.
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let left = self.and(step1, context.new_rvalue_from_int(typ, 0x3333));
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let left = self.shl(left, context.new_rvalue_from_int(typ, 2));
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let right = self.and(step1, context.new_rvalue_from_int(typ, 0xCCCC));
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let right = self.lshr(right, context.new_rvalue_from_int(typ, 2));
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let step2 = self.or(left, right);
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// Third step.
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let left = self.and(step2, context.new_rvalue_from_int(typ, 0x0F0F));
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let left = self.shl(left, context.new_rvalue_from_int(typ, 4));
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let right = self.and(step2, context.new_rvalue_from_int(typ, 0xF0F0));
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let right = self.lshr(right, context.new_rvalue_from_int(typ, 4));
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let left = self.lshr(step2, four);
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let left = self.and(left, m2);
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let right = self.and(step2, m2);
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let right = self.shl(right, four);
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let step3 = self.or(left, right);
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// Fourth step.
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let left = self.and(step3, context.new_rvalue_from_int(typ, 0x00FF));
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let left = self.shl(left, context.new_rvalue_from_int(typ, 8));
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let right = self.and(step3, context.new_rvalue_from_int(typ, 0xFF00));
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let right = self.lshr(right, context.new_rvalue_from_int(typ, 8));
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let step4 = self.or(left, right);
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step4
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},
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32 => {
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// TODO(antoyo): Refactor with other implementations.
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// First step.
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let left = self.and(value, context.new_rvalue_from_long(typ, 0x55555555));
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let left = self.shl(left, context.new_rvalue_from_long(typ, 1));
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let right = self.and(value, context.new_rvalue_from_long(typ, 0xAAAAAAAA));
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let right = self.lshr(right, context.new_rvalue_from_long(typ, 1));
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let step1 = self.or(left, right);
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// Second step.
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let left = self.and(step1, context.new_rvalue_from_long(typ, 0x33333333));
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let left = self.shl(left, context.new_rvalue_from_long(typ, 2));
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let right = self.and(step1, context.new_rvalue_from_long(typ, 0xCCCCCCCC));
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let right = self.lshr(right, context.new_rvalue_from_long(typ, 2));
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let step2 = self.or(left, right);
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// Third step.
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let left = self.and(step2, context.new_rvalue_from_long(typ, 0x0F0F0F0F));
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let left = self.shl(left, context.new_rvalue_from_long(typ, 4));
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let right = self.and(step2, context.new_rvalue_from_long(typ, 0xF0F0F0F0));
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let right = self.lshr(right, context.new_rvalue_from_long(typ, 4));
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let step3 = self.or(left, right);
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// Fourth step.
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let left = self.and(step3, context.new_rvalue_from_long(typ, 0x00FF00FF));
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let left = self.shl(left, context.new_rvalue_from_long(typ, 8));
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let right = self.and(step3, context.new_rvalue_from_long(typ, 0xFF00FF00));
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let right = self.lshr(right, context.new_rvalue_from_long(typ, 8));
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let step4 = self.or(left, right);
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// Fifth step.
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let left = self.and(step4, context.new_rvalue_from_long(typ, 0x0000FFFF));
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let left = self.shl(left, context.new_rvalue_from_long(typ, 16));
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let right = self.and(step4, context.new_rvalue_from_long(typ, 0xFFFF0000));
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let right = self.lshr(right, context.new_rvalue_from_long(typ, 16));
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let step5 = self.or(left, right);
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||||
|
||||
step5
|
||||
},
|
||||
64 => {
|
||||
// First step.
|
||||
let left = self.shl(value, context.new_rvalue_from_long(typ, 32));
|
||||
let right = self.lshr(value, context.new_rvalue_from_long(typ, 32));
|
||||
let step1 = self.or(left, right);
|
||||
|
||||
// Second step.
|
||||
let left = self.and(step1, context.new_rvalue_from_long(typ, 0x0001FFFF0001FFFF));
|
||||
let left = self.shl(left, context.new_rvalue_from_long(typ, 15));
|
||||
let right = self.and(step1, context.new_rvalue_from_long(typ, 0xFFFE0000FFFE0000u64 as i64)); // TODO(antoyo): transmute the number instead?
|
||||
let right = self.lshr(right, context.new_rvalue_from_long(typ, 17));
|
||||
let step2 = self.or(left, right);
|
||||
|
||||
// Third step.
|
||||
let left = self.lshr(step2, context.new_rvalue_from_long(typ, 10));
|
||||
let left = self.xor(step2, left);
|
||||
let temp = self.and(left, context.new_rvalue_from_long(typ, 0x003F801F003F801F));
|
||||
|
||||
let left = self.shl(temp, context.new_rvalue_from_long(typ, 10));
|
||||
let left = self.or(temp, left);
|
||||
let step3 = self.xor(left, step2);
|
||||
|
||||
// Fourth step.
|
||||
let left = self.lshr(step3, context.new_rvalue_from_long(typ, 4));
|
||||
let left = self.xor(step3, left);
|
||||
let temp = self.and(left, context.new_rvalue_from_long(typ, 0x0E0384210E038421));
|
||||
|
||||
let left = self.shl(temp, context.new_rvalue_from_long(typ, 4));
|
||||
let left = self.or(temp, left);
|
||||
let step4 = self.xor(left, step3);
|
||||
|
||||
// Fifth step.
|
||||
let left = self.lshr(step4, context.new_rvalue_from_long(typ, 2));
|
||||
let left = self.xor(step4, left);
|
||||
let temp = self.and(left, context.new_rvalue_from_long(typ, 0x2248884222488842));
|
||||
|
||||
let left = self.shl(temp, context.new_rvalue_from_long(typ, 2));
|
||||
let left = self.or(temp, left);
|
||||
let step5 = self.xor(left, step4);
|
||||
|
||||
step5
|
||||
if width == 8 {
|
||||
step3
|
||||
} else {
|
||||
self.gcc_bswap(step3, width)
|
||||
}
|
||||
},
|
||||
128 => {
|
||||
// TODO(antoyo): find a more efficient implementation?
|
||||
|
|
|
|||
|
|
@ -165,10 +165,15 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(
|
|||
InvalidMonomorphizationReturnIntegerType { span, name, ret_ty, out_ty }
|
||||
);
|
||||
|
||||
let arg1 = args[0].immediate();
|
||||
// NOTE: we get different vector types for the same vector type and libgccjit doesn't
|
||||
// compare them as equal, so bitcast.
|
||||
// FIXME(antoyo): allow comparing vector types as equal in libgccjit.
|
||||
let arg2 = bx.context.new_bitcast(None, args[1].immediate(), arg1.get_type());
|
||||
return Ok(compare_simd_types(
|
||||
bx,
|
||||
args[0].immediate(),
|
||||
args[1].immediate(),
|
||||
arg1,
|
||||
arg2,
|
||||
in_elem,
|
||||
llret_ty,
|
||||
cmp_op,
|
||||
|
|
@ -341,7 +346,8 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(
|
|||
// endian and MSB-first for big endian.
|
||||
|
||||
let vector = args[0].immediate();
|
||||
let vector_type = vector.get_type().dyncast_vector().expect("vector type");
|
||||
// TODO(antoyo): dyncast_vector should not require a call to unqualified.
|
||||
let vector_type = vector.get_type().unqualified().dyncast_vector().expect("vector type");
|
||||
let elem_type = vector_type.get_element_type();
|
||||
|
||||
let expected_int_bits = in_len.max(8);
|
||||
|
|
@ -848,7 +854,8 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(
|
|||
(true, true) => {
|
||||
// Algorithm from: https://codereview.stackexchange.com/questions/115869/saturated-signed-addition
|
||||
// TODO(antoyo): improve using conditional operators if possible.
|
||||
let arg_type = lhs.get_type();
|
||||
// TODO(antoyo): dyncast_vector should not require a call to unqualified.
|
||||
let arg_type = lhs.get_type().unqualified();
|
||||
// TODO(antoyo): convert lhs and rhs to unsigned.
|
||||
let sum = lhs + rhs;
|
||||
let vector_type = arg_type.dyncast_vector().expect("vector type");
|
||||
|
|
@ -878,7 +885,8 @@ pub fn generic_simd_intrinsic<'a, 'gcc, 'tcx>(
|
|||
res & cmp
|
||||
},
|
||||
(true, false) => {
|
||||
let arg_type = lhs.get_type();
|
||||
// TODO(antoyo): dyncast_vector should not require a call to unqualified.
|
||||
let arg_type = lhs.get_type().unqualified();
|
||||
// TODO(antoyo): this uses the same algorithm from saturating add, but add the
|
||||
// negative of the right operand. Find a proper subtraction algorithm.
|
||||
let rhs = bx.context.new_unary_op(None, UnaryOp::Minus, arg_type, rhs);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue