Rollup merge of #121841 - tgross35:f16-f128-step2-intrinsics, r=compiler-errors
`f16` and `f128` step 2: intrinsics Continuation of https://github.com/rust-lang/rust/pull/121728, another portion of https://github.com/rust-lang/rust/pull/114607. This PR adds `f16` and `f128` intrinsics, and hooks them up to both HIR and LLVM. This is all still unexposed to the frontend, which will probably be the next step. Also update itanium mangling per `@rcvalle's` in https://github.com/rust-lang/rust/pull/121728/files#r1506570300, and fix a typo from step 1. Once these types are usable in code, I will add the codegen tests from #114607 (codegen is passing on that branch) This does add more `unimplemented!`s to Clippy, but I still don't think we can do better until library support is added. r? `@compiler-errors` cc `@Nilstrieb` `@rustbot` label +T-compiler +F-f16_and_f128
This commit is contained in:
Guillaume Boisseau
GitHub
commit
4c65eef269
14 changed files with 273 additions and 10 deletions
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@ -112,11 +112,15 @@ pub fn intrinsic_operation_unsafety(tcx: TyCtxt<'_>, intrinsic_id: LocalDefId) -
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| sym::likely
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| sym::unlikely
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| sym::ptr_guaranteed_cmp
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| sym::minnumf16
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| sym::minnumf32
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| sym::minnumf64
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| sym::minnumf128
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| sym::maxnumf16
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| sym::maxnumf32
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| sym::rustc_peek
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| sym::maxnumf64
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| sym::maxnumf128
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| sym::rustc_peek
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| sym::type_name
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| sym::forget
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| sym::black_box
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@ -302,50 +306,118 @@ pub fn check_intrinsic_type(
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],
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Ty::new_unit(tcx),
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),
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sym::sqrtf16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
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sym::sqrtf32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
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sym::sqrtf64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
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sym::sqrtf128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
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sym::powif16 => (0, 0, vec![tcx.types.f16, tcx.types.i32], tcx.types.f16),
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sym::powif32 => (0, 0, vec![tcx.types.f32, tcx.types.i32], tcx.types.f32),
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sym::powif64 => (0, 0, vec![tcx.types.f64, tcx.types.i32], tcx.types.f64),
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sym::powif128 => (0, 0, vec![tcx.types.f128, tcx.types.i32], tcx.types.f128),
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sym::sinf16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
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sym::sinf32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
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sym::sinf64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
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sym::sinf128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
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sym::cosf16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
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sym::cosf32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
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sym::cosf64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
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sym::cosf128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
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sym::powf16 => (0, 0, vec![tcx.types.f16, tcx.types.f16], tcx.types.f16),
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sym::powf32 => (0, 0, vec![tcx.types.f32, tcx.types.f32], tcx.types.f32),
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sym::powf64 => (0, 0, vec![tcx.types.f64, tcx.types.f64], tcx.types.f64),
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sym::powf128 => (0, 0, vec![tcx.types.f128, tcx.types.f128], tcx.types.f128),
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sym::expf16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
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sym::expf32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
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sym::expf64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
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sym::expf128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
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sym::exp2f16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
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sym::exp2f32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
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sym::exp2f64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
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sym::exp2f128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
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sym::logf16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
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sym::logf32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
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sym::logf64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
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sym::logf128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
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sym::log10f16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
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sym::log10f32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
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sym::log10f64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
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sym::log10f128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
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sym::log2f16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
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sym::log2f32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
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sym::log2f64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
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sym::log2f128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
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sym::fmaf16 => (0, 0, vec![tcx.types.f16, tcx.types.f16, tcx.types.f16], tcx.types.f16),
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sym::fmaf32 => (0, 0, vec![tcx.types.f32, tcx.types.f32, tcx.types.f32], tcx.types.f32),
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sym::fmaf64 => (0, 0, vec![tcx.types.f64, tcx.types.f64, tcx.types.f64], tcx.types.f64),
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sym::fmaf128 => {
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(0, 0, vec![tcx.types.f128, tcx.types.f128, tcx.types.f128], tcx.types.f128)
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}
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sym::fabsf16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
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sym::fabsf32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
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sym::fabsf64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
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sym::fabsf128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
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sym::minnumf16 => (0, 0, vec![tcx.types.f16, tcx.types.f16], tcx.types.f16),
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sym::minnumf32 => (0, 0, vec![tcx.types.f32, tcx.types.f32], tcx.types.f32),
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sym::minnumf64 => (0, 0, vec![tcx.types.f64, tcx.types.f64], tcx.types.f64),
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sym::minnumf128 => (0, 0, vec![tcx.types.f128, tcx.types.f128], tcx.types.f128),
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sym::maxnumf16 => (0, 0, vec![tcx.types.f16, tcx.types.f16], tcx.types.f16),
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sym::maxnumf32 => (0, 0, vec![tcx.types.f32, tcx.types.f32], tcx.types.f32),
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sym::maxnumf64 => (0, 0, vec![tcx.types.f64, tcx.types.f64], tcx.types.f64),
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sym::maxnumf128 => (0, 0, vec![tcx.types.f128, tcx.types.f128], tcx.types.f128),
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sym::copysignf16 => (0, 0, vec![tcx.types.f16, tcx.types.f16], tcx.types.f16),
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sym::copysignf32 => (0, 0, vec![tcx.types.f32, tcx.types.f32], tcx.types.f32),
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sym::copysignf64 => (0, 0, vec![tcx.types.f64, tcx.types.f64], tcx.types.f64),
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sym::copysignf128 => (0, 0, vec![tcx.types.f128, tcx.types.f128], tcx.types.f128),
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sym::floorf16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
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sym::floorf32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
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sym::floorf64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
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sym::floorf128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
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sym::ceilf16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
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sym::ceilf32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
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sym::ceilf64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
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sym::ceilf128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
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sym::truncf16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
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sym::truncf32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
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sym::truncf64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
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sym::truncf128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
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sym::rintf16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
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sym::rintf32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
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sym::rintf64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
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sym::rintf128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
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sym::nearbyintf16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
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sym::nearbyintf32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
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sym::nearbyintf64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
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sym::nearbyintf128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
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sym::roundf16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
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sym::roundf32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
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sym::roundf64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
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sym::roundf128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
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sym::roundevenf16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
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sym::roundevenf32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
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sym::roundevenf64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
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sym::roundevenf128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
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sym::volatile_load | sym::unaligned_volatile_load => {
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(1, 0, vec![Ty::new_imm_ptr(tcx, param(0))], param(0))
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