Merge commit 'e228f0c16e
' into libgccjit-codegen
This commit is contained in:
commit
3d5d4e324d
27 changed files with 265 additions and 3053 deletions
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@ -15,106 +15,8 @@ use crate::type_of::LayoutGccExt;
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impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> {
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fn codegen_llvm_inline_asm(&mut self, _ia: &LlvmInlineAsmInner, _outputs: Vec<PlaceRef<'tcx, RValue<'gcc>>>, mut _inputs: Vec<RValue<'gcc>>, _span: Span) -> bool {
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// TODO
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// TODO(antoyo)
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return true;
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/*let mut ext_constraints = vec![];
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let mut output_types = vec![];
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// Prepare the output operands
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let mut indirect_outputs = vec![];
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for (i, (out, &place)) in ia.outputs.iter().zip(&outputs).enumerate() {
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if out.is_rw {
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let operand = self.load_operand(place);
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if let OperandValue::Immediate(_) = operand.val {
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inputs.push(operand.immediate());
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}
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ext_constraints.push(i.to_string());
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}
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if out.is_indirect {
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let operand = self.load_operand(place);
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if let OperandValue::Immediate(_) = operand.val {
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indirect_outputs.push(operand.immediate());
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}
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} else {
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output_types.push(place.layout.gcc_type(self.cx()));
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}
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}
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if !indirect_outputs.is_empty() {
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indirect_outputs.extend_from_slice(&inputs);
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inputs = indirect_outputs;
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}
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let clobbers = ia.clobbers.iter().map(|s| format!("~{{{}}}", &s));
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// Default per-arch clobbers
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// Basically what clang does
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let arch_clobbers = match &self.sess().target.target.arch[..] {
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"x86" | "x86_64" => vec!["~{dirflag}", "~{fpsr}", "~{flags}"],
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"mips" | "mips64" => vec!["~{$1}"],
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_ => Vec::new(),
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};
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let all_constraints = ia
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.outputs
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.iter()
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.map(|out| out.constraint.to_string())
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.chain(ia.inputs.iter().map(|s| s.to_string()))
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.chain(ext_constraints)
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.chain(clobbers)
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.chain(arch_clobbers.iter().map(|s| (*s).to_string()))
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.collect::<Vec<String>>()
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.join(",");
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debug!("Asm Constraints: {}", &all_constraints);
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// Depending on how many outputs we have, the return type is different
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let num_outputs = output_types.len();
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let output_type = match num_outputs {
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0 => self.type_void(),
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1 => output_types[0],
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_ => self.type_struct(&output_types, false),
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};
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let asm = ia.asm.as_str();
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let r = inline_asm_call(
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self,
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&asm,
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&all_constraints,
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&inputs,
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output_type,
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ia.volatile,
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ia.alignstack,
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ia.dialect,
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);
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if r.is_none() {
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return false;
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}
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let r = r.unwrap();
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// Again, based on how many outputs we have
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let outputs = ia.outputs.iter().zip(&outputs).filter(|&(ref o, _)| !o.is_indirect);
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for (i, (_, &place)) in outputs.enumerate() {
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let v = if num_outputs == 1 { r } else { self.extract_value(r, i as u64) };
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OperandValue::Immediate(v).store(self, place);
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}
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// Store mark in a metadata node so we can map LLVM errors
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// back to source locations. See #17552.
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unsafe {
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let key = "srcloc";
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let kind = llvm::LLVMGetMDKindIDInContext(
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self.llcx,
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key.as_ptr() as *const c_char,
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key.len() as c_uint,
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);
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let val: &'ll Value = self.const_i32(span.ctxt().outer_expn().as_u32() as i32);
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llvm::LLVMSetMetadata(r, kind, llvm::LLVMMDNodeInContext(self.llcx, &val, 1));
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}
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true*/
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}
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fn codegen_inline_asm(&mut self, template: &[InlineAsmTemplatePiece], operands: &[InlineAsmOperandRef<'tcx, Self>], options: InlineAsmOptions, _span: &[Span]) {
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@ -127,7 +29,7 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> {
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};
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// Collect the types of output operands
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// FIXME: we do this here instead of later because of a bug in libgccjit where creating the
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// FIXME(antoyo): we do this here instead of later because of a bug in libgccjit where creating the
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// variable after the extended asm expression causes a segfault:
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// https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100380
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let mut output_vars = FxHashMap::default();
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@ -160,11 +62,6 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> {
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match out_place {
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Some(place) => place.layout.gcc_type(self.cx, false),
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None => {
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// If the output is discarded, we don't really care what
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// type is used. We're just using this to tell GCC to
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// reserve the register.
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//dummy_output_type(self.cx, reg.reg_class())
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// NOTE: if no output value, we should not create one.
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continue;
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},
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@ -251,9 +148,9 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> {
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template_str
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}
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else {
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// FIXME: this might break the "m" memory constraint:
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// FIXME(antoyo): this might break the "m" memory constraint:
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// https://stackoverflow.com/a/9347957/389119
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// TODO: only set on x86 platforms.
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// TODO(antoyo): only set on x86 platforms.
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format!(".att_syntax noprefix\n\t{}\n\t.intel_syntax noprefix", template_str)
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};
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let extended_asm = block.add_extended_asm(None, &template_str);
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@ -274,7 +171,6 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> {
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},
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};
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output_types.push(ty);
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//op_idx.insert(idx, constraints.len());
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let prefix = if late { "=" } else { "=&" };
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let constraint = format!("{}{}", prefix, reg_to_gcc(reg));
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@ -295,14 +191,13 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> {
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None => dummy_output_type(self.cx, reg.reg_class())
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};
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output_types.push(ty);
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//op_idx.insert(idx, constraints.len());
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// TODO: prefix of "+" for reading and writing?
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// TODO(antoyo): prefix of "+" for reading and writing?
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let prefix = if late { "=" } else { "=&" };
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let constraint = format!("{}{}", prefix, reg_to_gcc(reg));
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if out_place.is_some() {
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let var = output_vars[&idx];
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// TODO: also specify an output operand when out_place is none: that would
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// TODO(antoyo): also specify an output operand when out_place is none: that would
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// be the clobber but clobbers do not support general constraint like reg;
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// they only support named registers.
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// Not sure how we can do this. And the LLVM backend does not seem to add a
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@ -321,63 +216,6 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> {
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}
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}
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/*if !options.contains(InlineAsmOptions::PRESERVES_FLAGS) {
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match asm_arch {
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InlineAsmArch::AArch64 | InlineAsmArch::Arm => {
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constraints.push("~{cc}".to_string());
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}
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InlineAsmArch::X86 | InlineAsmArch::X86_64 => {
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constraints.extend_from_slice(&[
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"~{dirflag}".to_string(),
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"~{fpsr}".to_string(),
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"~{flags}".to_string(),
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]);
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}
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InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {}
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}
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}
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if !options.contains(InlineAsmOptions::NOMEM) {
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// This is actually ignored by LLVM, but it's probably best to keep
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// it just in case. LLVM instead uses the ReadOnly/ReadNone
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// attributes on the call instruction to optimize.
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constraints.push("~{memory}".to_string());
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}
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let volatile = !options.contains(InlineAsmOptions::PURE);
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let alignstack = !options.contains(InlineAsmOptions::NOSTACK);
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let output_type = match &output_types[..] {
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[] => self.type_void(),
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[ty] => ty,
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tys => self.type_struct(&tys, false),
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};*/
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/*let result = inline_asm_call(
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self,
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&template_str,
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&constraints.join(","),
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&inputs,
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output_type,
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volatile,
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alignstack,
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dialect,
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span,
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)
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.unwrap_or_else(|| span_bug!(span, "LLVM asm constraint validation failed"));
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if options.contains(InlineAsmOptions::PURE) {
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if options.contains(InlineAsmOptions::NOMEM) {
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llvm::Attribute::ReadNone.apply_callsite(llvm::AttributePlace::Function, result);
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} else if options.contains(InlineAsmOptions::READONLY) {
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llvm::Attribute::ReadOnly.apply_callsite(llvm::AttributePlace::Function, result);
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}
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} else {
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if options.contains(InlineAsmOptions::NOMEM) {
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llvm::Attribute::InaccessibleMemOnly
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.apply_callsite(llvm::AttributePlace::Function, result);
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} else {
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// LLVM doesn't have an attribute to represent ReadOnly + SideEffect
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}
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}*/
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// Write results to outputs
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for (idx, op) in operands.iter().enumerate() {
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if let InlineAsmOperandRef::Out { place: Some(place), .. }
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@ -390,12 +228,12 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> {
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}
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/// Converts a register class to a GCC constraint code.
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// TODO: return &'static str instead?
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// TODO(antoyo): return &'static str instead?
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fn reg_to_gcc(reg: InlineAsmRegOrRegClass) -> String {
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match reg {
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// For vector registers LLVM wants the register name to match the type size.
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InlineAsmRegOrRegClass::Reg(reg) => {
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// TODO: add support for vector register.
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// TODO(antoyo): add support for vector register.
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let constraint =
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match reg.name() {
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"ax" => "a",
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@ -404,11 +242,11 @@ fn reg_to_gcc(reg: InlineAsmRegOrRegClass) -> String {
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"dx" => "d",
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"si" => "S",
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"di" => "D",
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// TODO: for registers like r11, we have to create a register variable: https://stackoverflow.com/a/31774784/389119
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// TODO: in this case though, it's a clobber, so it should work as r11.
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// TODO(antoyo): for registers like r11, we have to create a register variable: https://stackoverflow.com/a/31774784/389119
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// TODO(antoyo): in this case though, it's a clobber, so it should work as r11.
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// Recent nightly supports clobber() syntax, so update to it. It does not seem
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// like it's implemented yet.
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name => name, // FIXME: probably wrong.
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name => name, // FIXME(antoyo): probably wrong.
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};
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constraint.to_string()
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},
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@ -570,7 +408,6 @@ fn modifier_to_gcc(arch: InlineAsmArch, reg: InlineAsmRegClass, modifier: Option
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InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg)
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| InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::vreg_low16) => {
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unimplemented!()
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//if modifier == Some('v') { None } else { modifier }
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}
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InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg)
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| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg_thumb) => unimplemented!(),
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@ -583,11 +420,6 @@ fn modifier_to_gcc(arch: InlineAsmArch, reg: InlineAsmRegClass, modifier: Option
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| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low8)
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| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low4) => {
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unimplemented!()
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/*if modifier.is_none() {
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Some('q')
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} else {
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modifier
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}*/
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}
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InlineAsmRegClass::Bpf(_) => unimplemented!(),
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InlineAsmRegClass::Hexagon(_) => unimplemented!(),
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@ -612,15 +444,7 @@ fn modifier_to_gcc(arch: InlineAsmArch, reg: InlineAsmRegClass, modifier: Option
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InlineAsmRegClass::X86(X86InlineAsmRegClass::reg_byte) => unimplemented!(),
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InlineAsmRegClass::X86(X86InlineAsmRegClass::xmm_reg)
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| InlineAsmRegClass::X86(X86InlineAsmRegClass::ymm_reg)
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| InlineAsmRegClass::X86(X86InlineAsmRegClass::zmm_reg) => unimplemented!() /*match (reg, modifier) {
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(X86InlineAsmRegClass::xmm_reg, None) => Some('x'),
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(X86InlineAsmRegClass::ymm_reg, None) => Some('t'),
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(X86InlineAsmRegClass::zmm_reg, None) => Some('g'),
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(_, Some('x')) => Some('x'),
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(_, Some('y')) => Some('t'),
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(_, Some('z')) => Some('g'),
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_ => unreachable!(),
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}*/,
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| InlineAsmRegClass::X86(X86InlineAsmRegClass::zmm_reg) => unimplemented!(),
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InlineAsmRegClass::X86(X86InlineAsmRegClass::x87_reg) => unimplemented!(),
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InlineAsmRegClass::X86(X86InlineAsmRegClass::kreg) => unimplemented!(),
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InlineAsmRegClass::Wasm(WasmInlineAsmRegClass::local) => unimplemented!(),
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