Rollup merge of #130630 - taiki-e:s390x-clobber-abi, r=Amanieu
Support clobber_abi and vector/access registers (clobber-only) in s390x inline assembly This supports `clobber_abi` which is one of the requirements of stabilization mentioned in #93335. This also supports vector registers (as `vreg`) and access registers (as `areg`) as clobber-only, which need to support clobbering of them to implement clobber_abi. Refs: - "1.2.1.1. Register Preservation Rules" section in ELF Application Binary Interface s390x Supplement, Version 1.6.1 (lzsabi_s390x.pdf in https://github.com/IBM/s390x-abi/releases/tag/v1.6.1) - Register definition in LLVM: - Vector registers https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td#L249 - Access registers https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td#L332 I have three questions: - ~~ELF Application Binary Interface s390x Supplement says that `cc` (condition code, bits 18-19 of PSW) is "Volatile". However, we do not have a register class for `cc` and instead mark `cc` as clobbered unless `preserves_flags` is specified (https://github.com/rust-lang/rust/pull/111331). Therefore, in the current implementation, if both `preserves_flags` and `clobber_abi` are specified, `cc` is not marked as clobbered. Is this okay? Or even if `preserves_flags` is used, should `cc` be marked as clobbered if `clobber_abi` is used?~~ UPDATE: resolved https://github.com/rust-lang/rust/pull/130630#issuecomment-2367923121 - ~~ELF Application Binary Interface s390x Supplement says that `pm` (program mask, bits 20-23 of PSW) is "Cleared". There does not appear to be any registers associated with this in either [LLVM](https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td) or [GCC](33ccc1314d/gcc/config/s390/s390.h (L407-L431)), so at this point I don't see any way other than to just ignore it. Is this okay as-is?~~ UPDATE: resolved https://github.com/rust-lang/rust/pull/130630#issuecomment-2367923121 - Is "areg" a good name for register class name for access registers? It may be a bit confusing between that and `reg_addr`, which uses the “a” constraint (https://github.com/rust-lang/rust/pull/119431)... Note: - GCC seems to [recognize only `a0` and `a1`](33ccc1314d/gcc/config/s390/s390.h (L428-L429)), and using `a[2-15]` [causes errors](https://godbolt.org/z/a46vx8jjn). Given that cg_gcc has a similar problem with other architecture (https://github.com/rust-lang/rustc_codegen_gcc/issues/485), I don't feel this is a blocker for this PR, but it is worth mentioning here. - `vreg` should be able to accept `#[repr(simd)]` types as input if the `vector` target feature added in https://github.com/rust-lang/rust/pull/127506 is enabled, but core_arch has no s390x vector type and both `#[repr(simd)]` and `core::simd` are unstable, so I have not implemented it in this PR. EDIT: And supporting it is probably more complex than doing the equivalent on other architectures... https://github.com/rust-lang/rust/pull/88245#issuecomment-905559591 cc `@uweigand` r? `@Amanieu` `@rustbot` label +O-SystemZ
This commit is contained in:
Guillaume Gomez
GitHub
commit
344b6a1668
7 changed files with 200 additions and 12 deletions
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@ -439,7 +439,7 @@ impl InlineAsmReg {
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Self::Hexagon(r) => r.overlapping_regs(|r| cb(Self::Hexagon(r))),
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Self::LoongArch(_) => cb(self),
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Self::Mips(_) => cb(self),
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Self::S390x(_) => cb(self),
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Self::S390x(r) => r.overlapping_regs(|r| cb(Self::S390x(r))),
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Self::Bpf(r) => r.overlapping_regs(|r| cb(Self::Bpf(r))),
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Self::Avr(r) => r.overlapping_regs(|r| cb(Self::Avr(r))),
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Self::Msp430(_) => cb(self),
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@ -892,6 +892,7 @@ pub enum InlineAsmClobberAbi {
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AArch64NoX18,
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RiscV,
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LoongArch,
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S390x,
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}
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impl InlineAsmClobberAbi {
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@ -941,6 +942,10 @@ impl InlineAsmClobberAbi {
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"C" | "system" => Ok(InlineAsmClobberAbi::LoongArch),
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_ => Err(&["C", "system"]),
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},
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InlineAsmArch::S390x => match name {
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"C" | "system" => Ok(InlineAsmClobberAbi::S390x),
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_ => Err(&["C", "system"]),
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},
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_ => Err(&[]),
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}
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}
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@ -1098,6 +1103,28 @@ impl InlineAsmClobberAbi {
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f16, f17, f18, f19, f20, f21, f22, f23,
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}
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},
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InlineAsmClobberAbi::S390x => clobbered_regs! {
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S390x S390xInlineAsmReg {
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r0, r1, r2, r3, r4, r5,
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r14,
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// f0-f7, v0-v7
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f0, f1, f2, f3, f4, f5, f6, f7,
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v0, v1, v2, v3, v4, v5, v6, v7,
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// Technically the left halves of v8-v15 (i.e., f8-f15) are saved, but
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// we have no way of expressing this using clobbers.
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v8, v9, v10, v11, v12, v13, v14, v15,
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// Other vector registers are volatile
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v16, v17, v18, v19, v20, v21, v22, v23,
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v24, v25, v26, v27, v28, v29, v30, v31,
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// a0-a1 are reserved, other access registers are volatile
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a2, a3, a4, a5, a6, a7,
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a8, a9, a10, a11, a12, a13, a14, a15,
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}
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},
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}
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}
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}
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@ -9,6 +9,8 @@ def_reg_class! {
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reg,
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reg_addr,
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freg,
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vreg,
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areg,
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}
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}
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@ -35,11 +37,13 @@ impl S390xInlineAsmRegClass {
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pub fn supported_types(
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self,
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arch: InlineAsmArch,
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_arch: InlineAsmArch,
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) -> &'static [(InlineAsmType, Option<Symbol>)] {
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match (self, arch) {
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(Self::reg | Self::reg_addr, _) => types! { _: I8, I16, I32, I64; },
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(Self::freg, _) => types! { _: F32, F64; },
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match self {
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Self::reg | Self::reg_addr => types! { _: I8, I16, I32, I64; },
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Self::freg => types! { _: F32, F64; },
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Self::vreg => &[],
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Self::areg => &[],
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}
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}
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}
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@ -76,6 +80,52 @@ def_regs! {
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f13: freg = ["f13"],
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f14: freg = ["f14"],
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f15: freg = ["f15"],
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v0: vreg = ["v0"],
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v1: vreg = ["v1"],
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v2: vreg = ["v2"],
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v3: vreg = ["v3"],
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v4: vreg = ["v4"],
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v5: vreg = ["v5"],
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v6: vreg = ["v6"],
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v7: vreg = ["v7"],
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v8: vreg = ["v8"],
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v9: vreg = ["v9"],
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v10: vreg = ["v10"],
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v11: vreg = ["v11"],
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v12: vreg = ["v12"],
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v13: vreg = ["v13"],
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v14: vreg = ["v14"],
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v15: vreg = ["v15"],
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v16: vreg = ["v16"],
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v17: vreg = ["v17"],
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v18: vreg = ["v18"],
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v19: vreg = ["v19"],
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v20: vreg = ["v20"],
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v21: vreg = ["v21"],
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v22: vreg = ["v22"],
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v23: vreg = ["v23"],
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v24: vreg = ["v24"],
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v25: vreg = ["v25"],
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v26: vreg = ["v26"],
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v27: vreg = ["v27"],
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v28: vreg = ["v28"],
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v29: vreg = ["v29"],
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v30: vreg = ["v30"],
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v31: vreg = ["v31"],
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a2: areg = ["a2"],
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a3: areg = ["a3"],
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a4: areg = ["a4"],
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a5: areg = ["a5"],
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a6: areg = ["a6"],
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a7: areg = ["a7"],
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a8: areg = ["a8"],
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a9: areg = ["a9"],
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a10: areg = ["a10"],
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a11: areg = ["a11"],
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a12: areg = ["a12"],
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a13: areg = ["a13"],
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a14: areg = ["a14"],
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a15: areg = ["a15"],
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#error = ["r11"] =>
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"The frame pointer cannot be used as an operand for inline asm",
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#error = ["r15"] =>
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@ -87,13 +137,8 @@ def_regs! {
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"c12", "c13", "c14", "c15"
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] =>
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"control registers are reserved by the kernel and cannot be used as operands for inline asm",
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#error = [
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"a0", "a1", "a2", "a3",
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"a4", "a5", "a6", "a7",
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"a8", "a9", "a10", "a11",
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"a12", "a13", "a14", "a15"
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] =>
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"access registers are not supported and cannot be used as operands for inline asm",
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#error = ["a0", "a1"] =>
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"a0 and a1 are reserved for system use and cannot be used as operands for inline asm",
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}
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}
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@ -106,4 +151,48 @@ impl S390xInlineAsmReg {
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) -> fmt::Result {
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write!(out, "%{}", self.name())
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}
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pub fn overlapping_regs(self, mut cb: impl FnMut(S390xInlineAsmReg)) {
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macro_rules! reg_conflicts {
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(
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$(
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$full:ident : $($field:ident)*
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),*;
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) => {
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match self {
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$(
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Self::$full => {
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cb(Self::$full);
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$(cb(Self::$field);)*
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}
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$(Self::$field)|* => {
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cb(Self::$full);
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cb(self);
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}
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)*
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r => cb(r),
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}
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};
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}
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// The left halves of v0-v15 are aliased to f0-f15.
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reg_conflicts! {
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v0 : f0,
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v1 : f1,
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v2 : f2,
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v3 : f3,
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v4 : f4,
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v5 : f5,
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v6 : f6,
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v7 : f7,
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v8 : f8,
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v9 : f9,
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v10 : f10,
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v11 : f11,
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v12 : f12,
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v13 : f13,
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v14 : f14,
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v15 : f15;
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}
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}
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}
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