Merge commit '11a0cceab9' into subtree-update_cg_gcc_2023-10-09
This commit is contained in:
Antoni Boucher
commit
30290c8b41
82 changed files with 2848 additions and 669 deletions
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@ -2254,6 +2254,42 @@ match name {
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"llvm.hexagon.prefetch" => "__builtin_HEXAGON_prefetch",
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"llvm.hexagon.vmemcpy" => "__builtin_hexagon_vmemcpy",
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"llvm.hexagon.vmemset" => "__builtin_hexagon_vmemset",
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// loongarch
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"llvm.loongarch.asrtgt.d" => "__builtin_loongarch_asrtgt_d",
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"llvm.loongarch.asrtle.d" => "__builtin_loongarch_asrtle_d",
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"llvm.loongarch.break" => "__builtin_loongarch_break",
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"llvm.loongarch.cacop.d" => "__builtin_loongarch_cacop_d",
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"llvm.loongarch.cacop.w" => "__builtin_loongarch_cacop_w",
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"llvm.loongarch.cpucfg" => "__builtin_loongarch_cpucfg",
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"llvm.loongarch.crc.w.b.w" => "__builtin_loongarch_crc_w_b_w",
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"llvm.loongarch.crc.w.d.w" => "__builtin_loongarch_crc_w_d_w",
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"llvm.loongarch.crc.w.h.w" => "__builtin_loongarch_crc_w_h_w",
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"llvm.loongarch.crc.w.w.w" => "__builtin_loongarch_crc_w_w_w",
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"llvm.loongarch.crcc.w.b.w" => "__builtin_loongarch_crcc_w_b_w",
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"llvm.loongarch.crcc.w.d.w" => "__builtin_loongarch_crcc_w_d_w",
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"llvm.loongarch.crcc.w.h.w" => "__builtin_loongarch_crcc_w_h_w",
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"llvm.loongarch.crcc.w.w.w" => "__builtin_loongarch_crcc_w_w_w",
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"llvm.loongarch.csrrd.d" => "__builtin_loongarch_csrrd_d",
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"llvm.loongarch.csrrd.w" => "__builtin_loongarch_csrrd_w",
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"llvm.loongarch.csrwr.d" => "__builtin_loongarch_csrwr_d",
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"llvm.loongarch.csrwr.w" => "__builtin_loongarch_csrwr_w",
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"llvm.loongarch.csrxchg.d" => "__builtin_loongarch_csrxchg_d",
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"llvm.loongarch.csrxchg.w" => "__builtin_loongarch_csrxchg_w",
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"llvm.loongarch.dbar" => "__builtin_loongarch_dbar",
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"llvm.loongarch.ibar" => "__builtin_loongarch_ibar",
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"llvm.loongarch.iocsrrd.b" => "__builtin_loongarch_iocsrrd_b",
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"llvm.loongarch.iocsrrd.d" => "__builtin_loongarch_iocsrrd_d",
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"llvm.loongarch.iocsrrd.h" => "__builtin_loongarch_iocsrrd_h",
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"llvm.loongarch.iocsrrd.w" => "__builtin_loongarch_iocsrrd_w",
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"llvm.loongarch.iocsrwr.b" => "__builtin_loongarch_iocsrwr_b",
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"llvm.loongarch.iocsrwr.d" => "__builtin_loongarch_iocsrwr_d",
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"llvm.loongarch.iocsrwr.h" => "__builtin_loongarch_iocsrwr_h",
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"llvm.loongarch.iocsrwr.w" => "__builtin_loongarch_iocsrwr_w",
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"llvm.loongarch.lddir.d" => "__builtin_loongarch_lddir_d",
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"llvm.loongarch.ldpte.d" => "__builtin_loongarch_ldpte_d",
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"llvm.loongarch.movfcsr2gr" => "__builtin_loongarch_movfcsr2gr",
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"llvm.loongarch.movgr2fcsr" => "__builtin_loongarch_movgr2fcsr",
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"llvm.loongarch.syscall" => "__builtin_loongarch_syscall",
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// mips
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"llvm.mips.absq.s.ph" => "__builtin_mips_absq_s_ph",
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"llvm.mips.absq.s.qb" => "__builtin_mips_absq_s_qb",
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@ -2954,6 +2990,8 @@ match name {
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"llvm.nvvm.barrier0.and" => "__nvvm_bar0_and",
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"llvm.nvvm.barrier0.or" => "__nvvm_bar0_or",
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"llvm.nvvm.barrier0.popc" => "__nvvm_bar0_popc",
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"llvm.nvvm.bf2h.rn" => "__nvvm_bf2h_rn",
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"llvm.nvvm.bf2h.rn.ftz" => "__nvvm_bf2h_rn_ftz",
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"llvm.nvvm.bitcast.d2ll" => "__nvvm_bitcast_d2ll",
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"llvm.nvvm.bitcast.f2i" => "__nvvm_bitcast_f2i",
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"llvm.nvvm.bitcast.i2f" => "__nvvm_bitcast_i2f",
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@ -3016,8 +3054,6 @@ match name {
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"llvm.nvvm.div.rz.ftz.f" => "__nvvm_div_rz_ftz_f",
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"llvm.nvvm.ex2.approx.d" => "__nvvm_ex2_approx_d",
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"llvm.nvvm.ex2.approx.f" => "__nvvm_ex2_approx_f",
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"llvm.nvvm.ex2.approx.f16" => "__nvvm_ex2_approx_f16",
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"llvm.nvvm.ex2.approx.f16x2" => "__nvvm_ex2_approx_f16x2",
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"llvm.nvvm.ex2.approx.ftz.f" => "__nvvm_ex2_approx_ftz_f",
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"llvm.nvvm.f2bf16.rn" => "__nvvm_f2bf16_rn",
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"llvm.nvvm.f2bf16.rn.relu" => "__nvvm_f2bf16_rn_relu",
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@ -3079,11 +3115,17 @@ match name {
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"llvm.nvvm.fma.rn.bf16x2" => "__nvvm_fma_rn_bf16x2",
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"llvm.nvvm.fma.rn.d" => "__nvvm_fma_rn_d",
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"llvm.nvvm.fma.rn.f" => "__nvvm_fma_rn_f",
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"llvm.nvvm.fma.rn.f16" => "__nvvm_fma_rn_f16",
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"llvm.nvvm.fma.rn.f16x2" => "__nvvm_fma_rn_f16x2",
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"llvm.nvvm.fma.rn.ftz.bf16" => "__nvvm_fma_rn_ftz_bf16",
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"llvm.nvvm.fma.rn.ftz.bf16x2" => "__nvvm_fma_rn_ftz_bf16x2",
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"llvm.nvvm.fma.rn.ftz.f" => "__nvvm_fma_rn_ftz_f",
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"llvm.nvvm.fma.rn.ftz.relu.bf16" => "__nvvm_fma_rn_ftz_relu_bf16",
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"llvm.nvvm.fma.rn.ftz.relu.bf16x2" => "__nvvm_fma_rn_ftz_relu_bf16x2",
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"llvm.nvvm.fma.rn.ftz.sat.bf16" => "__nvvm_fma_rn_ftz_sat_bf16",
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"llvm.nvvm.fma.rn.ftz.sat.bf16x2" => "__nvvm_fma_rn_ftz_sat_bf16x2",
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"llvm.nvvm.fma.rn.relu.bf16" => "__nvvm_fma_rn_relu_bf16",
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"llvm.nvvm.fma.rn.relu.bf16x2" => "__nvvm_fma_rn_relu_bf16x2",
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"llvm.nvvm.fma.rn.sat.bf16" => "__nvvm_fma_rn_sat_bf16",
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"llvm.nvvm.fma.rn.sat.bf16x2" => "__nvvm_fma_rn_sat_bf16x2",
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"llvm.nvvm.fma.rp.d" => "__nvvm_fma_rp_d",
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"llvm.nvvm.fma.rp.f" => "__nvvm_fma_rp_f",
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"llvm.nvvm.fma.rp.ftz.f" => "__nvvm_fma_rp_ftz_f",
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@ -3094,11 +3136,17 @@ match name {
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"llvm.nvvm.fmax.bf16x2" => "__nvvm_fmax_bf16x2",
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"llvm.nvvm.fmax.d" => "__nvvm_fmax_d",
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"llvm.nvvm.fmax.f" => "__nvvm_fmax_f",
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"llvm.nvvm.fmax.f16" => "__nvvm_fmax_f16",
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"llvm.nvvm.fmax.f16x2" => "__nvvm_fmax_f16x2",
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"llvm.nvvm.fmax.ftz.bf16" => "__nvvm_fmax_ftz_bf16",
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"llvm.nvvm.fmax.ftz.bf16x2" => "__nvvm_fmax_ftz_bf16x2",
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"llvm.nvvm.fmax.ftz.f" => "__nvvm_fmax_ftz_f",
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"llvm.nvvm.fmax.ftz.nan.bf16" => "__nvvm_fmax_ftz_nan_bf16",
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"llvm.nvvm.fmax.ftz.nan.bf16x2" => "__nvvm_fmax_ftz_nan_bf16x2",
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"llvm.nvvm.fmax.ftz.nan.f" => "__nvvm_fmax_ftz_nan_f",
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"llvm.nvvm.fmax.ftz.nan.xorsign.abs.bf16" => "__nvvm_fmax_ftz_nan_xorsign_abs_bf16",
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"llvm.nvvm.fmax.ftz.nan.xorsign.abs.bf16x2" => "__nvvm_fmax_ftz_nan_xorsign_abs_bf16x2",
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"llvm.nvvm.fmax.ftz.nan.xorsign.abs.f" => "__nvvm_fmax_ftz_nan_xorsign_abs_f",
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"llvm.nvvm.fmax.ftz.xorsign.abs.bf16" => "__nvvm_fmax_ftz_xorsign_abs_bf16",
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"llvm.nvvm.fmax.ftz.xorsign.abs.bf16x2" => "__nvvm_fmax_ftz_xorsign_abs_bf16x2",
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"llvm.nvvm.fmax.ftz.xorsign.abs.f" => "__nvvm_fmax_ftz_xorsign_abs_f",
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"llvm.nvvm.fmax.nan.bf16" => "__nvvm_fmax_nan_bf16",
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"llvm.nvvm.fmax.nan.bf16x2" => "__nvvm_fmax_nan_bf16x2",
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@ -3113,11 +3161,17 @@ match name {
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"llvm.nvvm.fmin.bf16x2" => "__nvvm_fmin_bf16x2",
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"llvm.nvvm.fmin.d" => "__nvvm_fmin_d",
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"llvm.nvvm.fmin.f" => "__nvvm_fmin_f",
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"llvm.nvvm.fmin.f16" => "__nvvm_fmin_f16",
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"llvm.nvvm.fmin.f16x2" => "__nvvm_fmin_f16x2",
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"llvm.nvvm.fmin.ftz.bf16" => "__nvvm_fmin_ftz_bf16",
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"llvm.nvvm.fmin.ftz.bf16x2" => "__nvvm_fmin_ftz_bf16x2",
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"llvm.nvvm.fmin.ftz.f" => "__nvvm_fmin_ftz_f",
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"llvm.nvvm.fmin.ftz.nan.bf16" => "__nvvm_fmin_ftz_nan_bf16",
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"llvm.nvvm.fmin.ftz.nan.bf16x2" => "__nvvm_fmin_ftz_nan_bf16x2",
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"llvm.nvvm.fmin.ftz.nan.f" => "__nvvm_fmin_ftz_nan_f",
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"llvm.nvvm.fmin.ftz.nan.xorsign.abs.bf16" => "__nvvm_fmin_ftz_nan_xorsign_abs_bf16",
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"llvm.nvvm.fmin.ftz.nan.xorsign.abs.bf16x2" => "__nvvm_fmin_ftz_nan_xorsign_abs_bf16x2",
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"llvm.nvvm.fmin.ftz.nan.xorsign.abs.f" => "__nvvm_fmin_ftz_nan_xorsign_abs_f",
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"llvm.nvvm.fmin.ftz.xorsign.abs.bf16" => "__nvvm_fmin_ftz_xorsign_abs_bf16",
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"llvm.nvvm.fmin.ftz.xorsign.abs.bf16x2" => "__nvvm_fmin_ftz_xorsign_abs_bf16x2",
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"llvm.nvvm.fmin.ftz.xorsign.abs.f" => "__nvvm_fmin_ftz_xorsign_abs_f",
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"llvm.nvvm.fmin.nan.bf16" => "__nvvm_fmin_nan_bf16",
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"llvm.nvvm.fmin.nan.bf16x2" => "__nvvm_fmin_nan_bf16x2",
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@ -4213,6 +4267,28 @@ match name {
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"llvm.r600.read.tgid.x" => "__builtin_r600_read_tgid_x",
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"llvm.r600.read.tgid.y" => "__builtin_r600_read_tgid_y",
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"llvm.r600.read.tgid.z" => "__builtin_r600_read_tgid_z",
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// riscv
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"llvm.riscv.aes32dsi" => "__builtin_riscv_aes32dsi",
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"llvm.riscv.aes32dsmi" => "__builtin_riscv_aes32dsmi",
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"llvm.riscv.aes32esi" => "__builtin_riscv_aes32esi",
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"llvm.riscv.aes32esmi" => "__builtin_riscv_aes32esmi",
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"llvm.riscv.aes64ds" => "__builtin_riscv_aes64ds",
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"llvm.riscv.aes64dsm" => "__builtin_riscv_aes64dsm",
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"llvm.riscv.aes64es" => "__builtin_riscv_aes64es",
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"llvm.riscv.aes64esm" => "__builtin_riscv_aes64esm",
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"llvm.riscv.aes64im" => "__builtin_riscv_aes64im",
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"llvm.riscv.aes64ks1i" => "__builtin_riscv_aes64ks1i",
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"llvm.riscv.aes64ks2" => "__builtin_riscv_aes64ks2",
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"llvm.riscv.sha512sig0" => "__builtin_riscv_sha512sig0",
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"llvm.riscv.sha512sig0h" => "__builtin_riscv_sha512sig0h",
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"llvm.riscv.sha512sig0l" => "__builtin_riscv_sha512sig0l",
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"llvm.riscv.sha512sig1" => "__builtin_riscv_sha512sig1",
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"llvm.riscv.sha512sig1h" => "__builtin_riscv_sha512sig1h",
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"llvm.riscv.sha512sig1l" => "__builtin_riscv_sha512sig1l",
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"llvm.riscv.sha512sum0" => "__builtin_riscv_sha512sum0",
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"llvm.riscv.sha512sum0r" => "__builtin_riscv_sha512sum0r",
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"llvm.riscv.sha512sum1" => "__builtin_riscv_sha512sum1",
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"llvm.riscv.sha512sum1r" => "__builtin_riscv_sha512sum1r",
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// s390
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"llvm.s390.efpc" => "__builtin_s390_efpc",
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"llvm.s390.etnd" => "__builtin_tx_nesting_depth",
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@ -5912,6 +5988,18 @@ match name {
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"llvm.x86.avx2.vpdpbuud.256" => "__builtin_ia32_vpdpbuud256",
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"llvm.x86.avx2.vpdpbuuds.128" => "__builtin_ia32_vpdpbuuds128",
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"llvm.x86.avx2.vpdpbuuds.256" => "__builtin_ia32_vpdpbuuds256",
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"llvm.x86.avx2.vpdpwsud.128" => "__builtin_ia32_vpdpwsud128",
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"llvm.x86.avx2.vpdpwsud.256" => "__builtin_ia32_vpdpwsud256",
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"llvm.x86.avx2.vpdpwsuds.128" => "__builtin_ia32_vpdpwsuds128",
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"llvm.x86.avx2.vpdpwsuds.256" => "__builtin_ia32_vpdpwsuds256",
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"llvm.x86.avx2.vpdpwusd.128" => "__builtin_ia32_vpdpwusd128",
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"llvm.x86.avx2.vpdpwusd.256" => "__builtin_ia32_vpdpwusd256",
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"llvm.x86.avx2.vpdpwusds.128" => "__builtin_ia32_vpdpwusds128",
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"llvm.x86.avx2.vpdpwusds.256" => "__builtin_ia32_vpdpwusds256",
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"llvm.x86.avx2.vpdpwuud.128" => "__builtin_ia32_vpdpwuud128",
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"llvm.x86.avx2.vpdpwuud.256" => "__builtin_ia32_vpdpwuud256",
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"llvm.x86.avx2.vpdpwuuds.128" => "__builtin_ia32_vpdpwuuds128",
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"llvm.x86.avx2.vpdpwuuds.256" => "__builtin_ia32_vpdpwuuds256",
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"llvm.x86.avx2.vperm2i128" => "__builtin_ia32_permti256",
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"llvm.x86.avx512.add.pd.512" => "__builtin_ia32_addpd512",
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"llvm.x86.avx512.add.ps.512" => "__builtin_ia32_addps512",
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@ -7909,6 +7997,16 @@ match name {
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"llvm.x86.vgf2p8mulb.128" => "__builtin_ia32_vgf2p8mulb_v16qi",
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"llvm.x86.vgf2p8mulb.256" => "__builtin_ia32_vgf2p8mulb_v32qi",
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"llvm.x86.vgf2p8mulb.512" => "__builtin_ia32_vgf2p8mulb_v64qi",
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"llvm.x86.vsha512msg1" => "__builtin_ia32_vsha512msg1",
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"llvm.x86.vsha512msg2" => "__builtin_ia32_vsha512msg2",
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"llvm.x86.vsha512rnds2" => "__builtin_ia32_vsha512rnds2",
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"llvm.x86.vsm3msg1" => "__builtin_ia32_vsm3msg1",
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"llvm.x86.vsm3msg2" => "__builtin_ia32_vsm3msg2",
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"llvm.x86.vsm3rnds2" => "__builtin_ia32_vsm3rnds2",
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"llvm.x86.vsm4key4128" => "__builtin_ia32_vsm4key4128",
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"llvm.x86.vsm4key4256" => "__builtin_ia32_vsm4key4256",
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"llvm.x86.vsm4rnds4128" => "__builtin_ia32_vsm4rnds4128",
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"llvm.x86.vsm4rnds4256" => "__builtin_ia32_vsm4rnds4256",
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"llvm.x86.wbinvd" => "__builtin_ia32_wbinvd",
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"llvm.x86.wbnoinvd" => "__builtin_ia32_wbnoinvd",
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"llvm.x86.wrfsbase.32" => "__builtin_ia32_wrfsbase32",
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@ -236,11 +236,17 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc
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let arg2 = builder.context.new_cast(None, arg2, arg2_type);
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args = vec![new_args[0], arg2].into();
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},
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// These builtins are sent one more argument than needed.
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"__builtin_prefetch" => {
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let mut new_args = args.to_vec();
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new_args.pop();
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args = new_args.into();
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},
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// The GCC version returns one value of the tuple through a pointer.
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"__builtin_ia32_rdrand64_step" => {
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let arg = builder.current_func().new_local(None, builder.ulonglong_type, "return_rdrand_arg");
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args = vec![arg.get_address(None)].into();
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},
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_ => (),
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}
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}
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@ -361,6 +367,19 @@ pub fn adjust_intrinsic_return_value<'a, 'gcc, 'tcx>(builder: &Builder<'a, 'gcc,
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// builtin twice, we overwrite the return value with a dummy value.
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return_value = builder.context.new_rvalue_zero(builder.int_type);
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},
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"__builtin_ia32_rdrand64_step" => {
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let random_number = args[0].dereference(None).to_rvalue();
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let success_variable = builder.current_func().new_local(None, return_value.get_type(), "success");
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builder.llbb().add_assignment(None, success_variable, return_value);
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let field1 = builder.context.new_field(None, random_number.get_type(), "random_number");
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let field2 = builder.context.new_field(None, return_value.get_type(), "success");
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let struct_type = builder.context.new_struct_type(None, "rdrand_result", &[field1, field2]);
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return_value = builder.context.new_struct_constructor(None, struct_type.as_type(), None, &[
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random_number,
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success_variable.to_rvalue(),
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]);
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},
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_ => (),
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}
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@ -613,6 +632,7 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function
|
|||
"llvm.fshr.v8i16" => "__builtin_ia32_vpshrdv_v8hi",
|
||||
"llvm.x86.fma.vfmadd.sd" => "__builtin_ia32_vfmaddsd3",
|
||||
"llvm.x86.fma.vfmadd.ss" => "__builtin_ia32_vfmaddss3",
|
||||
"llvm.x86.rdrand.64" => "__builtin_ia32_rdrand64_step",
|
||||
|
||||
// The above doc points to unknown builtins for the following, so override them:
|
||||
"llvm.x86.avx2.gather.d.d" => "__builtin_ia32_gathersiv4si",
|
||||
|
|
|
|||
|
|
@ -10,9 +10,9 @@ use rustc_codegen_ssa::base::wants_msvc_seh;
|
|||
use rustc_codegen_ssa::common::IntPredicate;
|
||||
use rustc_codegen_ssa::mir::operand::{OperandRef, OperandValue};
|
||||
use rustc_codegen_ssa::mir::place::PlaceRef;
|
||||
use rustc_codegen_ssa::traits::{ArgAbiMethods, BaseTypeMethods, BuilderMethods, ConstMethods, IntrinsicCallMethods};
|
||||
use rustc_codegen_ssa::traits::{ArgAbiMethods, BuilderMethods, ConstMethods, IntrinsicCallMethods};
|
||||
#[cfg(feature="master")]
|
||||
use rustc_codegen_ssa::traits::MiscMethods;
|
||||
use rustc_codegen_ssa::traits::{BaseTypeMethods, MiscMethods};
|
||||
use rustc_codegen_ssa::errors::InvalidMonomorphization;
|
||||
use rustc_middle::bug;
|
||||
use rustc_middle::ty::{self, Instance, Ty};
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue