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Mark RISC-V vector state as clobbered in inline assembly

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This commit is contained in:
Amanieu d'Antras 2021-07-29 13:22:21 +02:00
parent e9fb7bada1
commit 2f4612260d
2 changed files with 9 additions and 1 deletions
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9
compiler/rustc_codegen_llvm/src/asm.rs
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@ -302,7 +302,14 @@ impl AsmBuilderMethods<'tcx> for Builder<'a, 'll, 'tcx> {
"~{flags}".to_string(),
]);
}
InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {}
InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {
constraints.extend_from_slice(&[
"~{vtype}".to_string(),
"~{vl}".to_string(),
"~{vxsat}".to_string(),
"~{vxrm}".to_string(),
]);
}
InlineAsmArch::Nvptx64 => {}
InlineAsmArch::PowerPC | InlineAsmArch::PowerPC64 => {}
InlineAsmArch::Hexagon => {}