Add support for Arm64EC inline assembly
This commit is contained in:
Daniel Paoliello
parent
5974fe87c4
commit
2e44d29460
5 changed files with 158 additions and 103 deletions
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@ -87,6 +87,20 @@ fn reserved_x18(
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}
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}
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fn restricted_for_arm64ec(
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arch: InlineAsmArch,
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_reloc_model: RelocModel,
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_target_features: &FxIndexSet<Symbol>,
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_target: &Target,
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_is_clobber: bool,
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) -> Result<(), &'static str> {
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if arch == InlineAsmArch::Arm64EC {
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Err("x13, x14, x23, x24, x28, v16-v31 cannot be used for Arm64EC")
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} else {
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Ok(())
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}
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}
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def_regs! {
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AArch64 AArch64InlineAsmReg AArch64InlineAsmRegClass {
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x0: reg = ["x0", "w0"],
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@ -102,8 +116,8 @@ def_regs! {
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x10: reg = ["x10", "w10"],
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x11: reg = ["x11", "w11"],
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x12: reg = ["x12", "w12"],
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x13: reg = ["x13", "w13"],
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x14: reg = ["x14", "w14"],
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x13: reg = ["x13", "w13"] % restricted_for_arm64ec,
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x14: reg = ["x14", "w14"] % restricted_for_arm64ec,
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x15: reg = ["x15", "w15"],
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x16: reg = ["x16", "w16"],
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x17: reg = ["x17", "w17"],
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@ -111,12 +125,12 @@ def_regs! {
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x20: reg = ["x20", "w20"],
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x21: reg = ["x21", "w21"],
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x22: reg = ["x22", "w22"],
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x23: reg = ["x23", "w23"],
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x24: reg = ["x24", "w24"],
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x23: reg = ["x23", "w23"] % restricted_for_arm64ec,
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x24: reg = ["x24", "w24"] % restricted_for_arm64ec,
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x25: reg = ["x25", "w25"],
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x26: reg = ["x26", "w26"],
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x27: reg = ["x27", "w27"],
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x28: reg = ["x28", "w28"],
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x28: reg = ["x28", "w28"] % restricted_for_arm64ec,
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x30: reg = ["x30", "w30", "lr", "wlr"],
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v0: vreg, vreg_low16 = ["v0", "b0", "h0", "s0", "d0", "q0", "z0"],
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v1: vreg, vreg_low16 = ["v1", "b1", "h1", "s1", "d1", "q1", "z1"],
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@ -134,22 +148,22 @@ def_regs! {
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v13: vreg, vreg_low16 = ["v13", "b13", "h13", "s13", "d13", "q13", "z13"],
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v14: vreg, vreg_low16 = ["v14", "b14", "h14", "s14", "d14", "q14", "z14"],
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v15: vreg, vreg_low16 = ["v15", "b15", "h15", "s15", "d15", "q15", "z15"],
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v16: vreg = ["v16", "b16", "h16", "s16", "d16", "q16", "z16"],
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v17: vreg = ["v17", "b17", "h17", "s17", "d17", "q17", "z17"],
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v18: vreg = ["v18", "b18", "h18", "s18", "d18", "q18", "z18"],
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v19: vreg = ["v19", "b19", "h19", "s19", "d19", "q19", "z19"],
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v20: vreg = ["v20", "b20", "h20", "s20", "d20", "q20", "z20"],
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v21: vreg = ["v21", "b21", "h21", "s21", "d21", "q21", "z21"],
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v22: vreg = ["v22", "b22", "h22", "s22", "d22", "q22", "z22"],
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v23: vreg = ["v23", "b23", "h23", "s23", "d23", "q23", "z23"],
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v24: vreg = ["v24", "b24", "h24", "s24", "d24", "q24", "z24"],
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v25: vreg = ["v25", "b25", "h25", "s25", "d25", "q25", "z25"],
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v26: vreg = ["v26", "b26", "h26", "s26", "d26", "q26", "z26"],
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v27: vreg = ["v27", "b27", "h27", "s27", "d27", "q27", "z27"],
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v28: vreg = ["v28", "b28", "h28", "s28", "d28", "q28", "z28"],
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v29: vreg = ["v29", "b29", "h29", "s29", "d29", "q29", "z29"],
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v30: vreg = ["v30", "b30", "h30", "s30", "d30", "q30", "z30"],
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v31: vreg = ["v31", "b31", "h31", "s31", "d31", "q31", "z31"],
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v16: vreg = ["v16", "b16", "h16", "s16", "d16", "q16", "z16"] % restricted_for_arm64ec,
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v17: vreg = ["v17", "b17", "h17", "s17", "d17", "q17", "z17"] % restricted_for_arm64ec,
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v18: vreg = ["v18", "b18", "h18", "s18", "d18", "q18", "z18"] % restricted_for_arm64ec,
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v19: vreg = ["v19", "b19", "h19", "s19", "d19", "q19", "z19"] % restricted_for_arm64ec,
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v20: vreg = ["v20", "b20", "h20", "s20", "d20", "q20", "z20"] % restricted_for_arm64ec,
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v21: vreg = ["v21", "b21", "h21", "s21", "d21", "q21", "z21"] % restricted_for_arm64ec,
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v22: vreg = ["v22", "b22", "h22", "s22", "d22", "q22", "z22"] % restricted_for_arm64ec,
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v23: vreg = ["v23", "b23", "h23", "s23", "d23", "q23", "z23"] % restricted_for_arm64ec,
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v24: vreg = ["v24", "b24", "h24", "s24", "d24", "q24", "z24"] % restricted_for_arm64ec,
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v25: vreg = ["v25", "b25", "h25", "s25", "d25", "q25", "z25"] % restricted_for_arm64ec,
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v26: vreg = ["v26", "b26", "h26", "s26", "d26", "q26", "z26"] % restricted_for_arm64ec,
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v27: vreg = ["v27", "b27", "h27", "s27", "d27", "q27", "z27"] % restricted_for_arm64ec,
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v28: vreg = ["v28", "b28", "h28", "s28", "d28", "q28", "z28"] % restricted_for_arm64ec,
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v29: vreg = ["v29", "b29", "h29", "s29", "d29", "q29", "z29"] % restricted_for_arm64ec,
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v30: vreg = ["v30", "b30", "h30", "s30", "d30", "q30", "z30"] % restricted_for_arm64ec,
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v31: vreg = ["v31", "b31", "h31", "s31", "d31", "q31", "z31"] % restricted_for_arm64ec,
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p0: preg = ["p0"],
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p1: preg = ["p1"],
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p2: preg = ["p2"],
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@ -217,6 +217,7 @@ pub enum InlineAsmArch {
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X86_64,
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Arm,
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AArch64,
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Arm64EC,
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RiscV32,
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RiscV64,
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Nvptx64,
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@ -246,6 +247,7 @@ impl FromStr for InlineAsmArch {
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"x86_64" => Ok(Self::X86_64),
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"arm" => Ok(Self::Arm),
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"aarch64" => Ok(Self::AArch64),
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"arm64ec" => Ok(Self::Arm64EC),
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"riscv32" => Ok(Self::RiscV32),
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"riscv64" => Ok(Self::RiscV64),
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"nvptx64" => Ok(Self::Nvptx64),
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@ -341,7 +343,9 @@ impl InlineAsmReg {
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Ok(match arch {
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InlineAsmArch::X86 | InlineAsmArch::X86_64 => Self::X86(X86InlineAsmReg::parse(name)?),
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InlineAsmArch::Arm => Self::Arm(ArmInlineAsmReg::parse(name)?),
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InlineAsmArch::AArch64 => Self::AArch64(AArch64InlineAsmReg::parse(name)?),
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InlineAsmArch::AArch64 | InlineAsmArch::Arm64EC => {
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Self::AArch64(AArch64InlineAsmReg::parse(name)?)
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}
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InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {
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Self::RiscV(RiscVInlineAsmReg::parse(name)?)
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}
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@ -610,7 +614,9 @@ impl InlineAsmRegClass {
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Self::X86(X86InlineAsmRegClass::parse(name)?)
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}
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InlineAsmArch::Arm => Self::Arm(ArmInlineAsmRegClass::parse(name)?),
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InlineAsmArch::AArch64 => Self::AArch64(AArch64InlineAsmRegClass::parse(name)?),
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InlineAsmArch::AArch64 | InlineAsmArch::Arm64EC => {
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Self::AArch64(AArch64InlineAsmRegClass::parse(name)?)
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}
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InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {
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Self::RiscV(RiscVInlineAsmRegClass::parse(name)?)
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}
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@ -783,7 +789,7 @@ pub fn allocatable_registers(
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arm::fill_reg_map(arch, reloc_model, target_features, target, &mut map);
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map
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}
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InlineAsmArch::AArch64 => {
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InlineAsmArch::AArch64 | InlineAsmArch::Arm64EC => {
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let mut map = aarch64::regclass_map();
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aarch64::fill_reg_map(arch, reloc_model, target_features, target, &mut map);
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map
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@ -909,6 +915,10 @@ impl InlineAsmClobberAbi {
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}),
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_ => Err(&["C", "system", "efiapi"]),
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},
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InlineAsmArch::Arm64EC => match name {
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"C" | "system" => Ok(InlineAsmClobberAbi::AArch64NoX18),
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_ => Err(&["C", "system"]),
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},
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InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => match name {
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"C" | "system" | "efiapi" => Ok(InlineAsmClobberAbi::RiscV),
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_ => Err(&["C", "system", "efiapi"]),
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