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[RISCV] Enable LLVM backend.

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David Craven 2018-07-24 12:03:28 +02:00
parent 8c069ceba8
commit 2d5f62fb48
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GPG key ID: 33B9E9FDE28D2C23
4 changed files with 19 additions and 2 deletions
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config.toml.example
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@ -62,7 +62,7 @@
# not built by default and the experimental Rust compilation targets that depend
# on them will not work unless the user opts in to building them. By default the
# `WebAssembly` target is enabled when compiling LLVM from scratch.
#experimental-targets = "WebAssembly"
#experimental-targets = "WebAssembly;RISCV"
# Cap the number of parallel linker invocations when compiling LLVM.
# This can be useful when building LLVM with debug info, which significantly