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llvm: update riscv target feature to match LLVM 19

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In llvm/llvm-project@9067070d91 they ended
up largely reverting
llvm/llvm-project@e817966718. This means
the change we did in
rust-lang/rust@b378059e6b is now only
corrct for LLVM 18...so we have to adjust again.

@rustbot label: +llvm-main
This commit is contained in:
Augie Fackler 2024-04-17 15:05:29 -04:00
parent 00ed4edb44
commit 22b704bac4
4 changed files with 8 additions and 7 deletions
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7
compiler/rustc_codegen_llvm/src/llvm_util.rs
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@ -270,9 +270,10 @@ pub fn to_llvm_features<'a>(sess: &Session, s: &'a str) -> LLVMFeature<'a> {
"sve2-bitperm",
TargetFeatureFoldStrength::EnableOnly("neon"),
),
// The unaligned-scalar-mem feature was renamed to fast-unaligned-access.
("riscv32" | "riscv64", "fast-unaligned-access") if get_version().0 <= 17 => {
LLVMFeature::new("unaligned-scalar-mem")
// In LLVM 18, `unaligned-scalar-mem` was merged with `unaligned-vector-mem` into a single feature called
// `fast-unaligned-access`. In LLVM 19, it was split back out.
("riscv32" | "riscv64", "unaligned-scalar-mem") if get_version().0 == 18 => {
LLVMFeature::new("fast-unaligned-access")
}
// For LLVM 18, enable the evex512 target feature if a avx512 target feature is enabled.
("x86", s) if get_version().0 >= 18 && s.starts_with("avx512") => {