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Rollup merge of #119431 - taiki-e:asm-s390x-reg-addr, r=Amanieu

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Support reg_addr register class in s390x inline assembly

In s390x, `r0` cannot be used as an address register (it is evaluated as zero in an address context).

Therefore, currently, in assemblies involving memory accesses, `r0` must be [marked as clobbered](1a1155653a/src/arch/s390x.rs (L58)) or [explicitly used to a non-address](1a1155653a/src/arch/s390x.rs (L135)) or explicitly use an address register to prevent `r0` from being allocated to a register for the address.

This patch adds a register class for allocating general-purpose registers, except `r0`, to make it easier to use address registers. (powerpc already has a register class (reg_nonzero) for a similar purpose.)

This is identical to the `a` constraint in LLVM and GCC:

https://llvm.org/docs/LangRef.html#supported-constraint-code-list
> a: A 32, 64, or 128-bit integer address register (excludes R0, which in an address context evaluates as zero).

https://gcc.gnu.org/onlinedocs/gcc/Machine-Constraints.html
> a
> Address register (general purpose register except r0)

cc ``@uweigand``

r? ``@Amanieu``
This commit is contained in:
Matthias Krüger 2024-01-04 15:33:59 +01:00 • committed by GitHub
commit 12c102ec53
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5 changed files with 50 additions and 18 deletions
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29
compiler/rustc_target/src/asm/s390x.rs
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@ -6,6 +6,7 @@ use std::fmt;
def_reg_class! {
S390x S390xInlineAsmRegClass {
reg,
reg_addr,
freg,
}
}
@ -36,7 +37,7 @@ impl S390xInlineAsmRegClass {
arch: InlineAsmArch,
) -> &'static [(InlineAsmType, Option<Symbol>)] {
match (self, arch) {
(Self::reg, _) => types! { _: I8, I16, I32, I64; },
(Self::reg | Self::reg_addr, _) => types! { _: I8, I16, I32, I64; },
(Self::freg, _) => types! { _: F32, F64; },
}
}
@ -45,19 +46,19 @@ impl S390xInlineAsmRegClass {
def_regs! {
S390x S390xInlineAsmReg S390xInlineAsmRegClass {
r0: reg = ["r0"],
r1: reg = ["r1"],
r2: reg = ["r2"],
r3: reg = ["r3"],
r4: reg = ["r4"],
r5: reg = ["r5"],
r6: reg = ["r6"],
r7: reg = ["r7"],
r8: reg = ["r8"],
r9: reg = ["r9"],
r10: reg = ["r10"],
r12: reg = ["r12"],
r13: reg = ["r13"],
r14: reg = ["r14"],
r1: reg, reg_addr = ["r1"],
r2: reg, reg_addr = ["r2"],
r3: reg, reg_addr = ["r3"],
r4: reg, reg_addr = ["r4"],
r5: reg, reg_addr = ["r5"],
r6: reg, reg_addr = ["r6"],
r7: reg, reg_addr = ["r7"],
r8: reg, reg_addr = ["r8"],
r9: reg, reg_addr = ["r9"],
r10: reg, reg_addr = ["r10"],
r12: reg, reg_addr = ["r12"],
r13: reg, reg_addr = ["r13"],
r14: reg, reg_addr = ["r14"],
f0: freg = ["f0"],
f1: freg = ["f1"],
f2: freg = ["f2"],