bjoernager/rust
bjoernager/rust
1
Fork 0
Code Activity

Support RISC-V unaligned-scalar-mem target feature

Browse source 
This adds `unaligned-scalar-mem` as an allowed RISC-V target feature.
Some RISC-V cores support unaligned access to memory without trapping.
On such cores, the compiler could significantly improve code-size and
performance when using functions like core::ptr::read_unaligned<u32>
by emitting a single load or store instruction with an unaligned
address, rather than a long sequence of byte load/store/bitmanip
instructions.

Enabling the `unaligned-scalar-mem` target feature allows LLVM to do
this optimization.

Fixes #110883
This commit is contained in:
Kor Nielsen 2023-04-26 23:56:55 -07:00
parent adaac6b166
commit 08f7e32a6e
1 changed files with 1 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

1
compiler/rustc_codegen_ssa/src/target_features.rs
View file

@ -252,6 +252,7 @@ const RISCV_ALLOWED_FEATURES: &[(&str, Option<Symbol>)] = &[
("f", Some(sym::riscv_target_feature)),
("m", Some(sym::riscv_target_feature)),
("relax", Some(sym::riscv_target_feature)),
("unaligned-scalar-mem", Some(sym::riscv_target_feature)),
("v", Some(sym::riscv_target_feature)),
("zba", Some(sym::riscv_target_feature)),
("zbb", Some(sym::riscv_target_feature)),