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Rollup merge of #104066 - TimNN:riscv-layout, r=nikic

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LLVM 16: Update RISCV data layout

The RISCV data layout was changed in 974e2e690b.

This updates all `riscv64*` targets, though I don't really know what the difference between the `gc` and `imac` ones is.

Passes `x test codegen` at LLVM head and with the currently bundled LLVM version. Without this patch, some tests fail with:

> error: internal compiler error: compiler/rustc_codegen_llvm/src/context.rs:192:13: data-layout for target `riscv64gc-unknown-none-elf`, `e-m:e-p:64:64-i64:64-i128:128-n64-S128`, differs from LLVM target's `riscv64` default layout, `e-m:e-p:64:64-i64:64-i128:128-n32:64-S128
This commit is contained in:
Yuki Okushi 2022-11-07 09:46:28 +09:00 • committed by GitHub
commit 02a0bdee0d
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7 changed files with 10 additions and 6 deletions
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4
compiler/rustc_codegen_llvm/src/context.rs
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@ -158,6 +158,10 @@ pub unsafe fn create_module<'ll>(
if sess.target.arch == "s390x" {
target_data_layout = target_data_layout.replace("-v128:64", "");
}
if sess.target.arch == "riscv64" {
target_data_layout = target_data_layout.replace("-n32:64-", "-n64-");
}
}
// Ensure the data-layout values hardcoded remain the defaults.