2024-11-07 17:42:49 +01:00
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//! Type-checking for the rust-intrinsic intrinsics that the compiler exposes.
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2015-08-06 11:29:26 -07:00
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2024-11-02 19:32:56 -07:00
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use rustc_abi::ExternAbi;
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2020-08-27 20:09:22 +10:00
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use rustc_errors::codes::*;
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2024-02-29 11:58:51 +11:00
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use rustc_errors::{DiagMessage, struct_span_code_err};
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2024-11-07 08:59:43 +01:00
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use rustc_hir::{self as hir, Safety};
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2024-05-08 16:40:46 +10:00
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use rustc_middle::bug;
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2020-03-29 16:41:09 +02:00
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use rustc_middle::traits::{ObligationCause, ObligationCauseCode};
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2023-07-05 20:13:26 +01:00
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use rustc_middle::ty::{self, Ty, TyCtxt};
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2024-01-31 14:05:14 +00:00
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use rustc_span::def_id::LocalDefId;
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2024-12-13 10:29:23 +11:00
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use rustc_span::{Span, Symbol, sym};
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2015-08-06 11:29:26 -07:00
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2023-09-17 20:13:05 +02:00
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use crate::check::check_function_signature;
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use crate::errors::{
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2021-09-11 14:47:28 +00:00
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UnrecognizedAtomicOperation, UnrecognizedIntrinsicFunction,
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2021-07-01 13:52:44 +02:00
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WrongNumberOfGenericArgumentsToIntrinsic,
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2024-07-29 08:13:50 +10:00
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};
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2019-06-11 23:35:39 +03:00
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fn equate_intrinsic_type<'tcx>(
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2019-06-14 00:48:52 +03:00
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tcx: TyCtxt<'tcx>,
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2024-01-31 14:05:14 +00:00
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span: Span,
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def_id: LocalDefId,
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2018-08-22 15:56:37 +02:00
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n_tps: usize,
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2021-06-08 20:38:43 +02:00
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n_lts: usize,
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2023-09-18 14:37:19 +00:00
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n_cts: usize,
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2020-12-16 22:36:14 -05:00
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sig: ty::PolyFnSig<'tcx>,
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2018-08-22 15:56:37 +02:00
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) {
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2024-07-07 11:18:35 +00:00
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let (generics, span) = match tcx.hir_node_by_def_id(def_id) {
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2025-01-04 11:30:31 +01:00
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hir::Node::Item(hir::Item { kind: hir::ItemKind::Fn { generics, .. }, .. })
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2024-01-31 14:28:40 +00:00
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| hir::Node::ForeignItem(hir::ForeignItem {
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2024-08-07 13:01:34 -04:00
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kind: hir::ForeignItemKind::Fn(_, _, generics),
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2024-01-31 14:05:14 +00:00
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..
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2024-07-07 11:18:35 +00:00
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}) => (tcx.generics_of(def_id), generics.span),
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2017-05-13 17:11:52 +03:00
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_ => {
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2024-01-31 14:05:14 +00:00
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struct_span_code_err!(tcx.dcx(), span, E0622, "intrinsic must be a function")
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.with_span_label(span, "expected a function")
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2017-05-13 17:11:52 +03:00
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.emit();
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return;
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}
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2021-06-08 20:38:43 +02:00
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};
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2024-07-07 11:18:35 +00:00
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let own_counts = generics.own_counts();
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2016-02-16 18:36:41 +02:00
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2021-07-01 13:52:44 +02:00
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let gen_count_ok = |found: usize, expected: usize, descr: &str| -> bool {
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if found != expected {
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2023-12-18 22:21:37 +11:00
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tcx.dcx().emit_err(WrongNumberOfGenericArgumentsToIntrinsic {
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2021-07-01 13:52:44 +02:00
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span,
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found,
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expected,
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descr,
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});
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false
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} else {
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true
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}
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};
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2016-08-25 01:24:49 +02:00
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2024-07-07 11:18:35 +00:00
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// the host effect param should be invisible as it shouldn't matter
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// whether effects is enabled for the intrinsic provider crate.
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2021-07-01 13:52:44 +02:00
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if gen_count_ok(own_counts.lifetimes, n_lts, "lifetime")
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&& gen_count_ok(own_counts.types, n_tps, "type")
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2024-10-20 20:22:11 +00:00
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&& gen_count_ok(own_counts.consts, n_cts, "const")
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2021-07-01 13:52:44 +02:00
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{
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2023-12-18 22:24:10 +08:00
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let _ = check_function_signature(
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2023-01-18 16:52:47 -07:00
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tcx,
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2024-01-31 14:05:14 +00:00
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ObligationCause::new(span, def_id, ObligationCauseCode::IntrinsicType),
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def_id.into(),
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2023-09-17 20:13:05 +02:00
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sig,
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2023-01-18 16:52:47 -07:00
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);
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2015-08-06 14:52:40 -07:00
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}
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}
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2015-08-06 11:29:26 -07:00
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2021-06-12 19:01:32 +02:00
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/// Returns the unsafety of the given intrinsic.
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2024-05-17 14:17:48 -03:00
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pub fn intrinsic_operation_unsafety(tcx: TyCtxt<'_>, intrinsic_id: LocalDefId) -> hir::Safety {
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2024-02-02 14:47:59 +00:00
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let has_safe_attr = if tcx.has_attr(intrinsic_id, sym::rustc_intrinsic) {
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2024-05-17 14:17:48 -03:00
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tcx.fn_sig(intrinsic_id).skip_binder().safety()
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2024-02-02 14:47:59 +00:00
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} else {
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2024-11-07 08:59:43 +01:00
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// Old-style intrinsics are never safe
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Safety::Unsafe
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2022-09-09 16:38:33 +02:00
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};
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2024-01-31 14:05:14 +00:00
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let is_in_list = match tcx.item_name(intrinsic_id.into()) {
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2022-09-09 16:38:33 +02:00
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// When adding a new intrinsic to this list,
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// it's usually worth updating that intrinsic's documentation
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// to note that it's safe to call, since
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// safe extern fns are otherwise unprecedented.
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sym::abort
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| sym::assert_inhabited
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| sym::assert_zero_valid
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2022-12-12 15:47:32 +01:00
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| sym::assert_mem_uninitialized_valid
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2025-01-02 21:22:42 +01:00
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| sym::box_new
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2024-12-01 19:07:13 -08:00
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| sym::breakpoint
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2022-09-09 16:38:33 +02:00
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| sym::size_of
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| sym::min_align_of
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| sym::needs_drop
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| sym::caller_location
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| sym::add_with_overflow
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| sym::sub_with_overflow
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| sym::mul_with_overflow
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2024-11-29 21:32:03 -08:00
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| sym::carrying_mul_add
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2022-09-09 16:38:33 +02:00
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| sym::wrapping_add
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| sym::wrapping_sub
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| sym::wrapping_mul
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| sym::saturating_add
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| sym::saturating_sub
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| sym::rotate_left
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| sym::rotate_right
|
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| sym::ctpop
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| sym::ctlz
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| sym::cttz
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| sym::bswap
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| sym::bitreverse
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2023-03-05 20:19:41 -08:00
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| sym::three_way_compare
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2022-09-09 16:38:33 +02:00
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| sym::discriminant_value
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| sym::type_id
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2024-07-26 19:36:21 +01:00
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| sym::select_unpredictable
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2024-07-26 15:51:46 +02:00
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| sym::cold_path
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2022-09-09 16:38:33 +02:00
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| sym::ptr_guaranteed_cmp
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2024-03-01 04:12:31 -05:00
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| sym::minnumf16
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2022-09-09 16:38:33 +02:00
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| sym::minnumf32
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| sym::minnumf64
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2024-03-01 04:12:31 -05:00
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| sym::minnumf128
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| sym::maxnumf16
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2022-09-09 16:38:33 +02:00
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| sym::maxnumf32
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| sym::maxnumf64
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2024-03-01 04:12:31 -05:00
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| sym::maxnumf128
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| sym::rustc_peek
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2022-09-09 16:38:33 +02:00
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| sym::type_name
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| sym::forget
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| sym::black_box
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| sym::variant_count
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2024-02-02 14:47:59 +00:00
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| sym::is_val_statically_known
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2024-02-07 10:26:00 -05:00
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| sym::ptr_mask
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2024-04-11 15:33:37 -07:00
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| sym::aggregate_raw_ptr
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2024-04-21 16:11:01 -07:00
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| sym::ptr_metadata
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2024-03-17 10:29:02 +01:00
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| sym::ub_checks
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2024-12-02 20:35:13 +00:00
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| sym::contract_checks
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| sym::contract_check_requires
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| sym::contract_check_ensures
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2024-02-06 14:32:00 -05:00
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| sym::fadd_algebraic
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| sym::fsub_algebraic
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| sym::fmul_algebraic
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| sym::fdiv_algebraic
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2024-03-02 12:53:28 +01:00
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| sym::frem_algebraic
|
2025-02-22 14:12:55 +01:00
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| sym::round_ties_even_f16
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| sym::round_ties_even_f32
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|
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| sym::round_ties_even_f64
|
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| sym::round_ties_even_f128
|
2024-05-17 14:17:48 -03:00
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| sym::const_eval_select => hir::Safety::Safe,
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_ => hir::Safety::Unsafe,
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2022-09-09 16:38:33 +02:00
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};
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|
|
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if has_safe_attr != is_in_list {
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2023-12-18 22:21:37 +11:00
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tcx.dcx().struct_span_err(
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2022-09-09 16:38:33 +02:00
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tcx.def_span(intrinsic_id),
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2024-02-29 11:58:51 +11:00
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DiagMessage::from(format!(
|
Use `Cow` in `{D,Subd}iagnosticMessage`.
Each of `{D,Subd}iagnosticMessage::{Str,Eager}` has a comment:
```
// FIXME(davidtwco): can a `Cow<'static, str>` be used here?
```
This commit answers that question in the affirmative. It's not the most
compelling change ever, but it might be worth merging.
This requires changing the `impl<'a> From<&'a str>` impls to `impl
From<&'static str>`, which involves a bunch of knock-on changes that
require/result in call sites being a little more precise about exactly
what kind of string they use to create errors, and not just `&str`. This
will result in fewer unnecessary allocations, though this will not have
any notable perf effects given that these are error paths.
Note that I was lazy within Clippy, using `to_string` in a few places to
preserve the existing string imprecision. I could have used `impl
Into<{D,Subd}iagnosticMessage>` in various places as is done in the
compiler, but that would have required changes to *many* call sites
(mostly changing `&format("...")` to `format!("...")`) which didn't seem
worthwhile.
2023-05-04 10:55:21 +10:00
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"intrinsic safety mismatch between list of intrinsics within the compiler and core library intrinsics for intrinsic `{}`",
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2024-01-31 14:05:14 +00:00
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tcx.item_name(intrinsic_id.into())
|
Use `Cow` in `{D,Subd}iagnosticMessage`.
Each of `{D,Subd}iagnosticMessage::{Str,Eager}` has a comment:
```
// FIXME(davidtwco): can a `Cow<'static, str>` be used here?
```
This commit answers that question in the affirmative. It's not the most
compelling change ever, but it might be worth merging.
This requires changing the `impl<'a> From<&'a str>` impls to `impl
From<&'static str>`, which involves a bunch of knock-on changes that
require/result in call sites being a little more precise about exactly
what kind of string they use to create errors, and not just `&str`. This
will result in fewer unnecessary allocations, though this will not have
any notable perf effects given that these are error paths.
Note that I was lazy within Clippy, using `to_string` in a few places to
preserve the existing string imprecision. I could have used `impl
Into<{D,Subd}iagnosticMessage>` in various places as is done in the
compiler, but that would have required changes to *many* call sites
(mostly changing `&format("...")` to `format!("...")`) which didn't seem
worthwhile.
2023-05-04 10:55:21 +10:00
|
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)
|
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)).emit();
|
2018-12-31 04:11:17 +01:00
|
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}
|
2022-09-09 16:38:33 +02:00
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|
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|
|
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is_in_list
|
2018-12-31 04:11:17 +01:00
|
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}
|
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|
2020-09-20 12:46:06 +00:00
|
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/// Remember to add all intrinsics here, in `compiler/rustc_codegen_llvm/src/intrinsic.rs`,
|
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/// and in `library/core/src/intrinsics.rs`.
|
2024-01-31 14:28:40 +00:00
|
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pub fn check_intrinsic_type(
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|
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|
tcx: TyCtxt<'_>,
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|
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|
intrinsic_id: LocalDefId,
|
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span: Span,
|
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intrinsic_name: Symbol,
|
2024-11-02 19:32:56 -07:00
|
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abi: ExternAbi,
|
2024-01-31 14:28:40 +00:00
|
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) {
|
2024-01-31 14:09:42 +00:00
|
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let generics = tcx.generics_of(intrinsic_id);
|
2024-02-03 18:52:30 +00:00
|
|
|
let param = |n| {
|
2024-04-19 22:59:34 -04:00
|
|
|
if let &ty::GenericParamDef { name, kind: ty::GenericParamDefKind::Type { .. }, .. } =
|
|
|
|
generics.param_at(n as usize, tcx)
|
2024-02-03 18:52:30 +00:00
|
|
|
{
|
|
|
|
Ty::new_param(tcx, n, name)
|
|
|
|
} else {
|
2024-01-31 14:09:42 +00:00
|
|
|
Ty::new_error_with_message(tcx, span, "expected param")
|
2024-02-03 18:52:30 +00:00
|
|
|
}
|
|
|
|
};
|
2020-06-28 12:58:20 +02:00
|
|
|
let name_str = intrinsic_name.as_str();
|
2018-10-23 23:13:33 +00:00
|
|
|
|
2023-02-17 14:33:08 +11:00
|
|
|
let bound_vars = tcx.mk_bound_variable_kinds(&[
|
2024-11-03 22:06:03 +00:00
|
|
|
ty::BoundVariableKind::Region(ty::BoundRegionKind::Anon),
|
|
|
|
ty::BoundVariableKind::Region(ty::BoundRegionKind::Anon),
|
|
|
|
ty::BoundVariableKind::Region(ty::BoundRegionKind::ClosureEnv),
|
2023-02-16 16:27:05 +11:00
|
|
|
]);
|
2019-03-25 14:28:03 -07:00
|
|
|
let mk_va_list_ty = |mutbl| {
|
2018-10-23 23:13:33 +00:00
|
|
|
tcx.lang_items().va_list().map(|did| {
|
2023-11-13 14:00:05 +00:00
|
|
|
let region = ty::Region::new_bound(
|
|
|
|
tcx,
|
|
|
|
ty::INNERMOST,
|
2024-11-03 22:06:03 +00:00
|
|
|
ty::BoundRegion { var: ty::BoundVar::ZERO, kind: ty::BoundRegionKind::Anon },
|
2023-02-13 13:03:45 +11:00
|
|
|
);
|
2023-11-13 14:00:05 +00:00
|
|
|
let env_region = ty::Region::new_bound(
|
|
|
|
tcx,
|
|
|
|
ty::INNERMOST,
|
|
|
|
ty::BoundRegion {
|
2023-11-27 22:36:39 -03:00
|
|
|
var: ty::BoundVar::from_u32(2),
|
2024-11-03 22:06:03 +00:00
|
|
|
kind: ty::BoundRegionKind::ClosureEnv,
|
2023-02-13 13:03:45 +11:00
|
|
|
},
|
|
|
|
);
|
2023-07-11 22:35:29 +01:00
|
|
|
let va_list_ty = tcx.type_of(did).instantiate(tcx, &[region.into()]);
|
2024-03-21 17:07:52 -04:00
|
|
|
(Ty::new_ref(tcx, env_region, va_list_ty, mutbl), va_list_ty)
|
2018-10-23 23:13:33 +00:00
|
|
|
})
|
|
|
|
};
|
|
|
|
|
2024-05-17 14:17:48 -03:00
|
|
|
let (n_tps, n_lts, n_cts, inputs, output, safety) = if name_str.starts_with("atomic_") {
|
2020-06-28 12:58:20 +02:00
|
|
|
let split: Vec<&str> = name_str.split('_').collect();
|
2018-09-19 13:51:51 +02:00
|
|
|
assert!(split.len() >= 2, "Atomic intrinsic in an incorrect format");
|
2015-08-06 11:29:26 -07:00
|
|
|
|
2025-01-29 14:27:02 +11:00
|
|
|
// Each atomic op has variants with different suffixes (`_seq_cst`, `_acquire`, etc.). Use
|
|
|
|
// string ops to strip the suffixes, because the variants all get the same treatment here.
|
2015-08-06 11:29:26 -07:00
|
|
|
let (n_tps, inputs, output) = match split[1] {
|
2016-10-04 02:19:40 +03:00
|
|
|
"cxchg" | "cxchgweak" => (
|
|
|
|
1,
|
2023-07-05 20:13:26 +01:00
|
|
|
vec![Ty::new_mut_ptr(tcx, param(0)), param(0), param(0)],
|
|
|
|
Ty::new_tup(tcx, &[param(0), tcx.types.bool]),
|
2019-12-22 17:42:04 -05:00
|
|
|
),
|
2023-07-05 20:13:26 +01:00
|
|
|
"load" => (1, vec![Ty::new_imm_ptr(tcx, param(0))], param(0)),
|
2024-05-02 17:49:23 +02:00
|
|
|
"store" => (1, vec![Ty::new_mut_ptr(tcx, param(0)), param(0)], tcx.types.unit),
|
2019-12-22 17:42:04 -05:00
|
|
|
|
2015-08-06 11:29:26 -07:00
|
|
|
"xchg" | "xadd" | "xsub" | "and" | "nand" | "or" | "xor" | "max" | "min" | "umax"
|
2023-07-05 20:13:26 +01:00
|
|
|
| "umin" => (1, vec![Ty::new_mut_ptr(tcx, param(0)), param(0)], param(0)),
|
2024-05-02 17:49:23 +02:00
|
|
|
"fence" | "singlethreadfence" => (0, Vec::new(), tcx.types.unit),
|
2015-08-06 11:29:26 -07:00
|
|
|
op => {
|
2024-01-31 14:09:42 +00:00
|
|
|
tcx.dcx().emit_err(UnrecognizedAtomicOperation { span, op });
|
2015-08-06 11:29:26 -07:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
};
|
2024-05-17 14:17:48 -03:00
|
|
|
(n_tps, 0, 0, inputs, output, hir::Safety::Unsafe)
|
2024-12-02 20:35:13 +00:00
|
|
|
} else if intrinsic_name == sym::contract_check_ensures {
|
2025-01-17 14:49:10 -08:00
|
|
|
// contract_check_ensures::<'a, Ret, C>(&'a Ret, C)
|
2024-12-02 20:35:13 +00:00
|
|
|
// where C: impl Fn(&'a Ret) -> bool,
|
|
|
|
//
|
2025-01-17 14:49:10 -08:00
|
|
|
// so: two type params, one lifetime param, 0 const params, two inputs, no return
|
2024-12-02 20:35:13 +00:00
|
|
|
|
|
|
|
let p = generics.param_at(0, tcx);
|
|
|
|
let r = ty::Region::new_early_param(tcx, p.to_early_bound_region_data());
|
|
|
|
let ref_ret = Ty::new_imm_ref(tcx, r, param(1));
|
2025-01-17 14:49:10 -08:00
|
|
|
(2, 1, 0, vec![ref_ret, param(2)], tcx.types.unit, hir::Safety::Safe)
|
2015-08-06 11:29:26 -07:00
|
|
|
} else {
|
2024-05-17 14:17:48 -03:00
|
|
|
let safety = intrinsic_operation_unsafety(tcx, intrinsic_id);
|
2024-01-31 14:22:10 +00:00
|
|
|
let (n_tps, n_cts, inputs, output) = match intrinsic_name {
|
|
|
|
sym::abort => (0, 0, vec![], tcx.types.never),
|
|
|
|
sym::unreachable => (0, 0, vec![], tcx.types.never),
|
2024-05-02 17:49:23 +02:00
|
|
|
sym::breakpoint => (0, 0, vec![], tcx.types.unit),
|
2020-06-28 12:58:20 +02:00
|
|
|
sym::size_of | sym::pref_align_of | sym::min_align_of | sym::variant_count => {
|
2024-01-31 14:22:10 +00:00
|
|
|
(1, 0, vec![], tcx.types.usize)
|
2020-06-23 16:46:24 +01:00
|
|
|
}
|
2020-06-28 12:58:20 +02:00
|
|
|
sym::size_of_val | sym::min_align_of_val => {
|
2024-01-31 14:22:10 +00:00
|
|
|
(1, 0, vec![Ty::new_imm_ptr(tcx, param(0))], tcx.types.usize)
|
2020-02-11 14:10:49 -05:00
|
|
|
}
|
2024-01-31 14:22:10 +00:00
|
|
|
sym::rustc_peek => (1, 0, vec![param(0)], param(0)),
|
|
|
|
sym::caller_location => (0, 0, vec![], tcx.caller_location_ty()),
|
2022-12-12 15:47:32 +01:00
|
|
|
sym::assert_inhabited
|
|
|
|
| sym::assert_zero_valid
|
2024-05-02 17:49:23 +02:00
|
|
|
| sym::assert_mem_uninitialized_valid => (1, 0, vec![], tcx.types.unit),
|
|
|
|
sym::forget => (1, 0, vec![param(0)], tcx.types.unit),
|
2024-01-31 14:22:10 +00:00
|
|
|
sym::transmute | sym::transmute_unchecked => (2, 0, vec![param(0)], param(1)),
|
2020-06-28 12:58:20 +02:00
|
|
|
sym::prefetch_read_data
|
|
|
|
| sym::prefetch_write_data
|
|
|
|
| sym::prefetch_read_instruction
|
2024-03-21 16:50:21 -04:00
|
|
|
| sym::prefetch_write_instruction => {
|
2024-05-02 17:49:23 +02:00
|
|
|
(1, 0, vec![Ty::new_imm_ptr(tcx, param(0)), tcx.types.i32], tcx.types.unit)
|
2024-03-21 16:50:21 -04:00
|
|
|
}
|
2024-01-31 14:22:10 +00:00
|
|
|
sym::needs_drop => (1, 0, vec![], tcx.types.bool),
|
2015-08-06 11:29:26 -07:00
|
|
|
|
2024-01-31 14:22:10 +00:00
|
|
|
sym::type_name => (1, 0, vec![], Ty::new_static_str(tcx)),
|
|
|
|
sym::type_id => (1, 0, vec![], tcx.types.u128),
|
|
|
|
sym::offset => (2, 0, vec![param(0), param(1)], param(0)),
|
2023-04-25 22:41:34 -07:00
|
|
|
sym::arith_offset => (
|
2015-08-06 11:29:26 -07:00
|
|
|
1,
|
2024-01-31 14:22:10 +00:00
|
|
|
0,
|
2024-03-21 16:50:21 -04:00
|
|
|
vec![Ty::new_imm_ptr(tcx, param(0)), tcx.types.isize],
|
|
|
|
Ty::new_imm_ptr(tcx, param(0)),
|
2019-12-22 17:42:04 -05:00
|
|
|
),
|
2022-05-11 17:52:00 +04:00
|
|
|
sym::ptr_mask => (
|
|
|
|
1,
|
2024-01-31 14:22:10 +00:00
|
|
|
0,
|
2024-03-21 16:50:21 -04:00
|
|
|
vec![Ty::new_imm_ptr(tcx, param(0)), tcx.types.usize],
|
|
|
|
Ty::new_imm_ptr(tcx, param(0)),
|
2022-05-11 17:52:00 +04:00
|
|
|
),
|
|
|
|
|
2020-06-28 12:58:20 +02:00
|
|
|
sym::copy | sym::copy_nonoverlapping => (
|
2019-12-22 17:42:04 -05:00
|
|
|
1,
|
2024-01-31 14:22:10 +00:00
|
|
|
0,
|
2016-10-29 22:54:04 +01:00
|
|
|
vec![
|
2024-03-21 16:50:21 -04:00
|
|
|
Ty::new_imm_ptr(tcx, param(0)),
|
|
|
|
Ty::new_mut_ptr(tcx, param(0)),
|
2016-10-04 02:19:40 +03:00
|
|
|
tcx.types.usize,
|
2016-10-29 22:54:04 +01:00
|
|
|
],
|
2024-05-02 17:49:23 +02:00
|
|
|
tcx.types.unit,
|
2016-10-04 02:19:40 +03:00
|
|
|
),
|
2020-06-28 12:58:20 +02:00
|
|
|
sym::volatile_copy_memory | sym::volatile_copy_nonoverlapping_memory => (
|
2015-08-06 11:29:26 -07:00
|
|
|
1,
|
2024-01-31 14:22:10 +00:00
|
|
|
0,
|
2016-10-29 22:54:04 +01:00
|
|
|
vec![
|
2024-03-21 16:50:21 -04:00
|
|
|
Ty::new_mut_ptr(tcx, param(0)),
|
|
|
|
Ty::new_imm_ptr(tcx, param(0)),
|
2015-08-06 11:29:26 -07:00
|
|
|
tcx.types.usize,
|
2019-12-22 17:42:04 -05:00
|
|
|
],
|
2024-05-02 17:49:23 +02:00
|
|
|
tcx.types.unit,
|
2019-12-22 17:42:04 -05:00
|
|
|
),
|
2023-08-02 12:45:52 -07:00
|
|
|
sym::compare_bytes => {
|
|
|
|
let byte_ptr = Ty::new_imm_ptr(tcx, tcx.types.u8);
|
2024-01-31 14:22:10 +00:00
|
|
|
(0, 0, vec![byte_ptr, byte_ptr, tcx.types.usize], tcx.types.i32)
|
2023-08-02 12:45:52 -07:00
|
|
|
}
|
2020-06-28 12:58:20 +02:00
|
|
|
sym::write_bytes | sym::volatile_set_memory => (
|
2019-12-22 17:42:04 -05:00
|
|
|
1,
|
2024-01-31 14:22:10 +00:00
|
|
|
0,
|
2024-03-21 16:50:21 -04:00
|
|
|
vec![Ty::new_mut_ptr(tcx, param(0)), tcx.types.u8, tcx.types.usize],
|
2024-05-02 17:49:23 +02:00
|
|
|
tcx.types.unit,
|
2019-12-22 17:42:04 -05:00
|
|
|
),
|
2024-03-01 04:12:31 -05:00
|
|
|
|
|
|
|
sym::sqrtf16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
|
2024-01-31 14:22:10 +00:00
|
|
|
sym::sqrtf32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
|
|
|
|
sym::sqrtf64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
|
2024-03-01 04:12:31 -05:00
|
|
|
sym::sqrtf128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
|
|
|
|
|
|
|
|
sym::powif16 => (0, 0, vec![tcx.types.f16, tcx.types.i32], tcx.types.f16),
|
2024-01-31 14:22:10 +00:00
|
|
|
sym::powif32 => (0, 0, vec![tcx.types.f32, tcx.types.i32], tcx.types.f32),
|
|
|
|
sym::powif64 => (0, 0, vec![tcx.types.f64, tcx.types.i32], tcx.types.f64),
|
2024-03-01 04:12:31 -05:00
|
|
|
sym::powif128 => (0, 0, vec![tcx.types.f128, tcx.types.i32], tcx.types.f128),
|
|
|
|
|
|
|
|
sym::sinf16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
|
2024-01-31 14:22:10 +00:00
|
|
|
sym::sinf32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
|
|
|
|
sym::sinf64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
|
2024-03-01 04:12:31 -05:00
|
|
|
sym::sinf128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
|
|
|
|
|
|
|
|
sym::cosf16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
|
2024-01-31 14:22:10 +00:00
|
|
|
sym::cosf32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
|
|
|
|
sym::cosf64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
|
2024-03-01 04:12:31 -05:00
|
|
|
sym::cosf128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
|
|
|
|
|
|
|
|
sym::powf16 => (0, 0, vec![tcx.types.f16, tcx.types.f16], tcx.types.f16),
|
2024-01-31 14:22:10 +00:00
|
|
|
sym::powf32 => (0, 0, vec![tcx.types.f32, tcx.types.f32], tcx.types.f32),
|
|
|
|
sym::powf64 => (0, 0, vec![tcx.types.f64, tcx.types.f64], tcx.types.f64),
|
2024-03-01 04:12:31 -05:00
|
|
|
sym::powf128 => (0, 0, vec![tcx.types.f128, tcx.types.f128], tcx.types.f128),
|
|
|
|
|
|
|
|
sym::expf16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
|
2024-01-31 14:22:10 +00:00
|
|
|
sym::expf32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
|
|
|
|
sym::expf64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
|
2024-03-01 04:12:31 -05:00
|
|
|
sym::expf128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
|
|
|
|
|
|
|
|
sym::exp2f16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
|
2024-01-31 14:22:10 +00:00
|
|
|
sym::exp2f32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
|
|
|
|
sym::exp2f64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
|
2024-03-01 04:12:31 -05:00
|
|
|
sym::exp2f128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
|
|
|
|
|
|
|
|
sym::logf16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
|
2024-01-31 14:22:10 +00:00
|
|
|
sym::logf32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
|
|
|
|
sym::logf64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
|
2024-03-01 04:12:31 -05:00
|
|
|
sym::logf128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
|
|
|
|
|
|
|
|
sym::log10f16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
|
2024-01-31 14:22:10 +00:00
|
|
|
sym::log10f32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
|
|
|
|
sym::log10f64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
|
2024-03-01 04:12:31 -05:00
|
|
|
sym::log10f128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
|
|
|
|
|
|
|
|
sym::log2f16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
|
2024-01-31 14:22:10 +00:00
|
|
|
sym::log2f32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
|
|
|
|
sym::log2f64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
|
2024-03-01 04:12:31 -05:00
|
|
|
sym::log2f128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
|
|
|
|
|
|
|
|
sym::fmaf16 => (0, 0, vec![tcx.types.f16, tcx.types.f16, tcx.types.f16], tcx.types.f16),
|
2024-01-31 14:22:10 +00:00
|
|
|
sym::fmaf32 => (0, 0, vec![tcx.types.f32, tcx.types.f32, tcx.types.f32], tcx.types.f32),
|
|
|
|
sym::fmaf64 => (0, 0, vec![tcx.types.f64, tcx.types.f64, tcx.types.f64], tcx.types.f64),
|
2024-03-01 04:12:31 -05:00
|
|
|
sym::fmaf128 => {
|
|
|
|
(0, 0, vec![tcx.types.f128, tcx.types.f128, tcx.types.f128], tcx.types.f128)
|
|
|
|
}
|
|
|
|
|
intrinsics.fmuladdf{16,32,64,128}: expose llvm.fmuladd.* semantics
Add intrinsics `fmuladd{f16,f32,f64,f128}`. This computes `(a * b) +
c`, to be fused if the code generator determines that (i) the target
instruction set has support for a fused operation, and (ii) that the
fused operation is more efficient than the equivalent, separate pair
of `mul` and `add` instructions.
https://llvm.org/docs/LangRef.html#llvm-fmuladd-intrinsic
MIRI support is included for f32 and f64.
The codegen_cranelift uses the `fma` function from libc, which is a
correct implementation, but without the desired performance semantic. I
think this requires an update to cranelift to expose a suitable
instruction in its IR.
I have not tested with codegen_gcc, but it should behave the same
way (using `fma` from libc).
2024-01-05 21:04:41 -07:00
|
|
|
sym::fmuladdf16 => {
|
|
|
|
(0, 0, vec![tcx.types.f16, tcx.types.f16, tcx.types.f16], tcx.types.f16)
|
|
|
|
}
|
|
|
|
sym::fmuladdf32 => {
|
|
|
|
(0, 0, vec![tcx.types.f32, tcx.types.f32, tcx.types.f32], tcx.types.f32)
|
|
|
|
}
|
|
|
|
sym::fmuladdf64 => {
|
|
|
|
(0, 0, vec![tcx.types.f64, tcx.types.f64, tcx.types.f64], tcx.types.f64)
|
|
|
|
}
|
|
|
|
sym::fmuladdf128 => {
|
|
|
|
(0, 0, vec![tcx.types.f128, tcx.types.f128, tcx.types.f128], tcx.types.f128)
|
|
|
|
}
|
|
|
|
|
2024-03-01 04:12:31 -05:00
|
|
|
sym::fabsf16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
|
2024-01-31 14:22:10 +00:00
|
|
|
sym::fabsf32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
|
|
|
|
sym::fabsf64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
|
2024-03-01 04:12:31 -05:00
|
|
|
sym::fabsf128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
|
|
|
|
|
|
|
|
sym::minnumf16 => (0, 0, vec![tcx.types.f16, tcx.types.f16], tcx.types.f16),
|
2024-01-31 14:22:10 +00:00
|
|
|
sym::minnumf32 => (0, 0, vec![tcx.types.f32, tcx.types.f32], tcx.types.f32),
|
|
|
|
sym::minnumf64 => (0, 0, vec![tcx.types.f64, tcx.types.f64], tcx.types.f64),
|
2024-03-01 04:12:31 -05:00
|
|
|
sym::minnumf128 => (0, 0, vec![tcx.types.f128, tcx.types.f128], tcx.types.f128),
|
|
|
|
|
|
|
|
sym::maxnumf16 => (0, 0, vec![tcx.types.f16, tcx.types.f16], tcx.types.f16),
|
2024-01-31 14:22:10 +00:00
|
|
|
sym::maxnumf32 => (0, 0, vec![tcx.types.f32, tcx.types.f32], tcx.types.f32),
|
|
|
|
sym::maxnumf64 => (0, 0, vec![tcx.types.f64, tcx.types.f64], tcx.types.f64),
|
2024-03-01 04:12:31 -05:00
|
|
|
sym::maxnumf128 => (0, 0, vec![tcx.types.f128, tcx.types.f128], tcx.types.f128),
|
|
|
|
|
|
|
|
sym::copysignf16 => (0, 0, vec![tcx.types.f16, tcx.types.f16], tcx.types.f16),
|
2024-01-31 14:22:10 +00:00
|
|
|
sym::copysignf32 => (0, 0, vec![tcx.types.f32, tcx.types.f32], tcx.types.f32),
|
|
|
|
sym::copysignf64 => (0, 0, vec![tcx.types.f64, tcx.types.f64], tcx.types.f64),
|
2024-03-01 04:12:31 -05:00
|
|
|
sym::copysignf128 => (0, 0, vec![tcx.types.f128, tcx.types.f128], tcx.types.f128),
|
|
|
|
|
|
|
|
sym::floorf16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
|
2024-01-31 14:22:10 +00:00
|
|
|
sym::floorf32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
|
|
|
|
sym::floorf64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
|
2024-03-01 04:12:31 -05:00
|
|
|
sym::floorf128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
|
|
|
|
|
|
|
|
sym::ceilf16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
|
2024-01-31 14:22:10 +00:00
|
|
|
sym::ceilf32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
|
|
|
|
sym::ceilf64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
|
2024-03-01 04:12:31 -05:00
|
|
|
sym::ceilf128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
|
|
|
|
|
|
|
|
sym::truncf16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
|
2024-01-31 14:22:10 +00:00
|
|
|
sym::truncf32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
|
|
|
|
sym::truncf64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
|
2024-03-01 04:12:31 -05:00
|
|
|
sym::truncf128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
|
|
|
|
|
2025-02-04 15:15:28 +01:00
|
|
|
sym::round_ties_even_f16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
|
|
|
|
sym::round_ties_even_f32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
|
|
|
|
sym::round_ties_even_f64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
|
|
|
|
sym::round_ties_even_f128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
|
2024-03-01 04:12:31 -05:00
|
|
|
|
|
|
|
sym::roundf16 => (0, 0, vec![tcx.types.f16], tcx.types.f16),
|
2024-01-31 14:22:10 +00:00
|
|
|
sym::roundf32 => (0, 0, vec![tcx.types.f32], tcx.types.f32),
|
|
|
|
sym::roundf64 => (0, 0, vec![tcx.types.f64], tcx.types.f64),
|
2024-03-01 04:12:31 -05:00
|
|
|
sym::roundf128 => (0, 0, vec![tcx.types.f128], tcx.types.f128),
|
2020-06-28 12:58:20 +02:00
|
|
|
|
|
|
|
sym::volatile_load | sym::unaligned_volatile_load => {
|
2024-01-31 14:22:10 +00:00
|
|
|
(1, 0, vec![Ty::new_imm_ptr(tcx, param(0))], param(0))
|
2015-08-06 11:29:26 -07:00
|
|
|
}
|
2020-06-28 12:58:20 +02:00
|
|
|
sym::volatile_store | sym::unaligned_volatile_store => {
|
2024-05-02 17:49:23 +02:00
|
|
|
(1, 0, vec![Ty::new_mut_ptr(tcx, param(0)), param(0)], tcx.types.unit)
|
2015-08-06 11:29:26 -07:00
|
|
|
}
|
2019-12-22 17:42:04 -05:00
|
|
|
|
2024-04-16 01:51:21 +00:00
|
|
|
sym::ctpop | sym::ctlz | sym::ctlz_nonzero | sym::cttz | sym::cttz_nonzero => {
|
|
|
|
(1, 0, vec![param(0)], tcx.types.u32)
|
|
|
|
}
|
|
|
|
|
|
|
|
sym::bswap | sym::bitreverse => (1, 0, vec![param(0)], param(0)),
|
2019-12-22 17:42:04 -05:00
|
|
|
|
2023-03-05 20:19:41 -08:00
|
|
|
sym::three_way_compare => {
|
|
|
|
(1, 0, vec![param(0), param(0)], tcx.ty_ordering_enum(Some(span)))
|
|
|
|
}
|
|
|
|
|
2020-06-28 12:58:20 +02:00
|
|
|
sym::add_with_overflow | sym::sub_with_overflow | sym::mul_with_overflow => {
|
2024-01-31 14:22:10 +00:00
|
|
|
(1, 0, vec![param(0), param(0)], Ty::new_tup(tcx, &[param(0), tcx.types.bool]))
|
2015-08-06 11:29:26 -07:00
|
|
|
}
|
2019-12-22 17:42:04 -05:00
|
|
|
|
2024-11-29 21:32:03 -08:00
|
|
|
sym::carrying_mul_add => {
|
|
|
|
(2, 0, vec![param(0); 4], Ty::new_tup(tcx, &[param(1), param(0)]))
|
|
|
|
}
|
|
|
|
|
2023-07-05 20:13:26 +01:00
|
|
|
sym::ptr_guaranteed_cmp => (
|
|
|
|
1,
|
2024-06-16 15:12:22 +00:00
|
|
|
0,
|
2023-07-05 20:13:26 +01:00
|
|
|
vec![Ty::new_imm_ptr(tcx, param(0)), Ty::new_imm_ptr(tcx, param(0))],
|
|
|
|
tcx.types.u8,
|
|
|
|
),
|
2020-06-16 10:37:34 +02:00
|
|
|
|
2020-12-01 15:39:25 +05:30
|
|
|
sym::const_allocate => {
|
2024-06-16 15:12:22 +00:00
|
|
|
(0, 0, vec![tcx.types.usize, tcx.types.usize], Ty::new_mut_ptr(tcx, tcx.types.u8))
|
2020-12-01 15:39:25 +05:30
|
|
|
}
|
2021-12-25 22:35:11 +09:00
|
|
|
sym::const_deallocate => (
|
2024-01-31 14:22:10 +00:00
|
|
|
0,
|
2024-06-16 15:12:22 +00:00
|
|
|
0,
|
2023-07-05 20:13:26 +01:00
|
|
|
vec![Ty::new_mut_ptr(tcx, tcx.types.u8), tcx.types.usize, tcx.types.usize],
|
2024-05-02 17:49:23 +02:00
|
|
|
tcx.types.unit,
|
2021-12-25 22:35:11 +09:00
|
|
|
),
|
2020-12-01 15:39:25 +05:30
|
|
|
|
2023-07-05 20:13:26 +01:00
|
|
|
sym::ptr_offset_from => (
|
|
|
|
1,
|
2024-01-31 14:22:10 +00:00
|
|
|
0,
|
2023-07-05 20:13:26 +01:00
|
|
|
vec![Ty::new_imm_ptr(tcx, param(0)), Ty::new_imm_ptr(tcx, param(0))],
|
|
|
|
tcx.types.isize,
|
|
|
|
),
|
|
|
|
sym::ptr_offset_from_unsigned => (
|
|
|
|
1,
|
2024-01-31 14:22:10 +00:00
|
|
|
0,
|
2023-07-05 20:13:26 +01:00
|
|
|
vec![Ty::new_imm_ptr(tcx, param(0)), Ty::new_imm_ptr(tcx, param(0))],
|
|
|
|
tcx.types.usize,
|
|
|
|
),
|
2025-01-19 23:38:09 -08:00
|
|
|
sym::unchecked_div | sym::unchecked_rem | sym::exact_div | sym::disjoint_bitor => {
|
2024-01-31 14:22:10 +00:00
|
|
|
(1, 0, vec![param(0), param(0)], param(0))
|
2015-08-06 11:29:26 -07:00
|
|
|
}
|
2024-03-30 00:36:45 -07:00
|
|
|
sym::unchecked_shl | sym::unchecked_shr => (2, 0, vec![param(0), param(1)], param(0)),
|
2024-04-16 01:51:21 +00:00
|
|
|
sym::rotate_left | sym::rotate_right => (1, 0, vec![param(0), tcx.types.u32], param(0)),
|
2020-06-28 12:58:20 +02:00
|
|
|
sym::unchecked_add | sym::unchecked_sub | sym::unchecked_mul => {
|
2024-01-31 14:22:10 +00:00
|
|
|
(1, 0, vec![param(0), param(0)], param(0))
|
2015-08-06 11:29:26 -07:00
|
|
|
}
|
2020-06-28 12:58:20 +02:00
|
|
|
sym::wrapping_add | sym::wrapping_sub | sym::wrapping_mul => {
|
2024-01-31 14:22:10 +00:00
|
|
|
(1, 0, vec![param(0), param(0)], param(0))
|
2015-08-06 11:29:26 -07:00
|
|
|
}
|
2024-01-31 14:22:10 +00:00
|
|
|
sym::saturating_add | sym::saturating_sub => (1, 0, vec![param(0), param(0)], param(0)),
|
2020-06-28 12:58:20 +02:00
|
|
|
sym::fadd_fast | sym::fsub_fast | sym::fmul_fast | sym::fdiv_fast | sym::frem_fast => {
|
2024-01-31 14:22:10 +00:00
|
|
|
(1, 0, vec![param(0), param(0)], param(0))
|
2015-08-06 11:29:26 -07:00
|
|
|
}
|
2024-02-06 14:32:00 -05:00
|
|
|
sym::fadd_algebraic
|
|
|
|
| sym::fsub_algebraic
|
|
|
|
| sym::fmul_algebraic
|
|
|
|
| sym::fdiv_algebraic
|
|
|
|
| sym::frem_algebraic => (1, 0, vec![param(0), param(0)], param(0)),
|
2024-01-31 14:22:10 +00:00
|
|
|
sym::float_to_int_unchecked => (2, 0, vec![param(0)], param(1)),
|
2015-08-06 11:29:26 -07:00
|
|
|
|
2024-06-16 15:12:22 +00:00
|
|
|
sym::assume => (0, 0, vec![tcx.types.bool], tcx.types.unit),
|
2024-07-26 19:36:21 +01:00
|
|
|
sym::select_unpredictable => (1, 0, vec![tcx.types.bool, param(0), param(0)], param(0)),
|
2024-07-26 15:51:46 +02:00
|
|
|
sym::cold_path => (0, 0, vec![], tcx.types.unit),
|
2015-08-06 11:29:26 -07:00
|
|
|
|
2024-01-31 14:22:10 +00:00
|
|
|
sym::read_via_copy => (1, 0, vec![Ty::new_imm_ptr(tcx, param(0))], param(0)),
|
2023-07-05 20:13:26 +01:00
|
|
|
sym::write_via_move => {
|
2024-05-02 17:49:23 +02:00
|
|
|
(1, 0, vec![Ty::new_mut_ptr(tcx, param(0)), param(0)], tcx.types.unit)
|
2023-07-05 20:13:26 +01:00
|
|
|
}
|
2023-03-11 15:32:54 -08:00
|
|
|
|
2024-12-25 10:49:23 +01:00
|
|
|
sym::typed_swap_nonoverlapping => {
|
|
|
|
(1, 0, vec![Ty::new_mut_ptr(tcx, param(0)); 2], tcx.types.unit)
|
|
|
|
}
|
2024-03-15 22:09:05 -07:00
|
|
|
|
2020-06-28 12:58:20 +02:00
|
|
|
sym::discriminant_value => {
|
2021-11-05 18:47:52 +00:00
|
|
|
let assoc_items = tcx.associated_item_def_ids(
|
|
|
|
tcx.require_lang_item(hir::LangItem::DiscriminantKind, None),
|
|
|
|
);
|
|
|
|
let discriminant_def_id = assoc_items[0];
|
2020-04-05 19:30:03 +02:00
|
|
|
|
2024-11-03 22:06:03 +00:00
|
|
|
let br =
|
|
|
|
ty::BoundRegion { var: ty::BoundVar::ZERO, kind: ty::BoundRegionKind::Anon };
|
2020-04-05 19:30:03 +02:00
|
|
|
(
|
|
|
|
1,
|
2024-01-31 14:22:10 +00:00
|
|
|
0,
|
2023-07-05 20:13:26 +01:00
|
|
|
vec![Ty::new_imm_ref(
|
|
|
|
tcx,
|
2023-11-13 14:00:05 +00:00
|
|
|
ty::Region::new_bound(tcx, ty::INNERMOST, br),
|
2023-07-05 20:13:26 +01:00
|
|
|
param(0),
|
|
|
|
)],
|
2024-06-21 13:33:08 -04:00
|
|
|
Ty::new_projection_from_args(
|
|
|
|
tcx,
|
|
|
|
discriminant_def_id,
|
|
|
|
tcx.mk_args(&[param(0).into()]),
|
|
|
|
),
|
2020-04-05 19:30:03 +02:00
|
|
|
)
|
|
|
|
}
|
2015-08-06 11:29:26 -07:00
|
|
|
|
2024-02-25 18:51:22 +01:00
|
|
|
sym::catch_unwind => {
|
2023-07-05 20:13:26 +01:00
|
|
|
let mut_u8 = Ty::new_mut_ptr(tcx, tcx.types.u8);
|
2020-10-07 20:02:06 -04:00
|
|
|
let try_fn_ty = ty::Binder::dummy(tcx.mk_fn_sig(
|
2023-02-16 16:05:08 +11:00
|
|
|
[mut_u8],
|
2024-05-02 17:49:23 +02:00
|
|
|
tcx.types.unit,
|
2017-02-13 10:51:06 +02:00
|
|
|
false,
|
2024-05-17 14:17:48 -03:00
|
|
|
hir::Safety::Safe,
|
2024-11-02 19:32:56 -07:00
|
|
|
ExternAbi::Rust,
|
2017-02-13 10:51:06 +02:00
|
|
|
));
|
2020-10-07 20:02:06 -04:00
|
|
|
let catch_fn_ty = ty::Binder::dummy(tcx.mk_fn_sig(
|
2023-02-16 16:05:08 +11:00
|
|
|
[mut_u8, mut_u8],
|
2024-05-02 17:49:23 +02:00
|
|
|
tcx.types.unit,
|
2020-03-02 13:59:20 +00:00
|
|
|
false,
|
2024-05-17 14:17:48 -03:00
|
|
|
hir::Safety::Safe,
|
2024-11-02 19:32:56 -07:00
|
|
|
ExternAbi::Rust,
|
2020-03-02 13:59:20 +00:00
|
|
|
));
|
|
|
|
(
|
2024-01-31 14:22:10 +00:00
|
|
|
0,
|
2020-03-02 13:59:20 +00:00
|
|
|
0,
|
2023-07-05 20:13:26 +01:00
|
|
|
vec![Ty::new_fn_ptr(tcx, try_fn_ty), mut_u8, Ty::new_fn_ptr(tcx, catch_fn_ty)],
|
2020-03-02 13:59:20 +00:00
|
|
|
tcx.types.i32,
|
|
|
|
)
|
2015-08-06 11:29:26 -07:00
|
|
|
}
|
|
|
|
|
2020-06-28 12:58:20 +02:00
|
|
|
sym::va_start | sym::va_end => match mk_va_list_ty(hir::Mutability::Mut) {
|
2024-05-02 17:49:23 +02:00
|
|
|
Some((va_list_ref_ty, _)) => (0, 0, vec![va_list_ref_ty], tcx.types.unit),
|
2024-04-17 12:30:45 +02:00
|
|
|
None => bug!("`va_list` lang item needed for C-variadic intrinsics"),
|
2018-10-23 23:13:33 +00:00
|
|
|
},
|
|
|
|
|
2020-06-28 12:58:20 +02:00
|
|
|
sym::va_copy => match mk_va_list_ty(hir::Mutability::Not) {
|
2019-03-25 14:28:03 -07:00
|
|
|
Some((va_list_ref_ty, va_list_ty)) => {
|
2023-07-05 20:13:26 +01:00
|
|
|
let va_list_ptr_ty = Ty::new_mut_ptr(tcx, va_list_ty);
|
2024-05-02 17:49:23 +02:00
|
|
|
(0, 0, vec![va_list_ptr_ty, va_list_ref_ty], tcx.types.unit)
|
2018-10-23 23:13:33 +00:00
|
|
|
}
|
2024-04-17 12:30:45 +02:00
|
|
|
None => bug!("`va_list` lang item needed for C-variadic intrinsics"),
|
2018-10-23 23:13:33 +00:00
|
|
|
},
|
|
|
|
|
2020-06-28 12:58:20 +02:00
|
|
|
sym::va_arg => match mk_va_list_ty(hir::Mutability::Mut) {
|
2024-01-31 14:22:10 +00:00
|
|
|
Some((va_list_ref_ty, _)) => (1, 0, vec![va_list_ref_ty], param(0)),
|
2024-04-17 12:30:45 +02:00
|
|
|
None => bug!("`va_list` lang item needed for C-variadic intrinsics"),
|
2018-10-23 23:13:33 +00:00
|
|
|
},
|
|
|
|
|
2023-07-05 20:13:26 +01:00
|
|
|
sym::nontemporal_store => {
|
2024-05-02 17:49:23 +02:00
|
|
|
(1, 0, vec![Ty::new_mut_ptr(tcx, param(0)), param(0)], tcx.types.unit)
|
2023-07-05 20:13:26 +01:00
|
|
|
}
|
2017-10-18 10:30:29 -07:00
|
|
|
|
2021-05-30 10:25:41 -07:00
|
|
|
sym::raw_eq => {
|
2024-11-03 22:06:03 +00:00
|
|
|
let br =
|
|
|
|
ty::BoundRegion { var: ty::BoundVar::ZERO, kind: ty::BoundRegionKind::Anon };
|
2023-11-27 22:36:39 -03:00
|
|
|
let param_ty_lhs =
|
|
|
|
Ty::new_imm_ref(tcx, ty::Region::new_bound(tcx, ty::INNERMOST, br), param(0));
|
2024-11-03 22:06:03 +00:00
|
|
|
let br = ty::BoundRegion {
|
|
|
|
var: ty::BoundVar::from_u32(1),
|
|
|
|
kind: ty::BoundRegionKind::Anon,
|
|
|
|
};
|
2023-11-27 22:36:39 -03:00
|
|
|
let param_ty_rhs =
|
2023-11-13 14:00:05 +00:00
|
|
|
Ty::new_imm_ref(tcx, ty::Region::new_bound(tcx, ty::INNERMOST, br), param(0));
|
2023-11-27 22:36:39 -03:00
|
|
|
(1, 0, vec![param_ty_lhs, param_ty_rhs], tcx.types.bool)
|
2021-05-30 10:25:41 -07:00
|
|
|
}
|
|
|
|
|
2024-01-31 14:22:10 +00:00
|
|
|
sym::black_box => (1, 0, vec![param(0)], param(0)),
|
2021-08-10 11:50:33 +01:00
|
|
|
|
2024-06-16 15:12:22 +00:00
|
|
|
sym::is_val_statically_known => (1, 0, vec![param(0)], tcx.types.bool),
|
2023-08-01 15:35:12 +00:00
|
|
|
|
2024-06-16 15:12:22 +00:00
|
|
|
sym::const_eval_select => (4, 0, vec![param(0), param(1), param(2)], param(3)),
|
2021-10-12 05:06:37 +00:00
|
|
|
|
2022-07-18 09:48:20 -04:00
|
|
|
sym::vtable_size | sym::vtable_align => {
|
2024-05-02 17:49:23 +02:00
|
|
|
(0, 0, vec![Ty::new_imm_ptr(tcx, tcx.types.unit)], tcx.types.usize)
|
2022-07-18 09:48:20 -04:00
|
|
|
}
|
|
|
|
|
2024-04-11 15:33:37 -07:00
|
|
|
// This type check is not particularly useful, but the `where` bounds
|
|
|
|
// on the definition in `core` do the heavy lifting for checking it.
|
2024-06-16 15:12:22 +00:00
|
|
|
sym::aggregate_raw_ptr => (3, 0, vec![param(1), param(2)], param(0)),
|
|
|
|
sym::ptr_metadata => (2, 0, vec![Ty::new_imm_ptr(tcx, param(0))], param(1)),
|
2024-04-11 15:33:37 -07:00
|
|
|
|
2024-06-16 15:12:22 +00:00
|
|
|
sym::ub_checks => (0, 0, Vec::new(), tcx.types.bool),
|
2024-02-07 10:26:00 -05:00
|
|
|
|
2025-01-02 21:22:42 +01:00
|
|
|
sym::box_new => (1, 0, vec![param(0)], Ty::new_box(tcx, param(0))),
|
|
|
|
|
2024-12-02 20:35:13 +00:00
|
|
|
// contract_checks() -> bool
|
|
|
|
sym::contract_checks => (0, 0, Vec::new(), tcx.types.bool),
|
|
|
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// contract_check_requires::<C>(C) -> bool, where C: impl Fn() -> bool
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2025-01-17 14:49:10 -08:00
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sym::contract_check_requires => (1, 0, vec![param(0)], tcx.types.unit),
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2024-12-02 20:35:13 +00:00
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2024-02-23 18:26:39 +01:00
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sym::simd_eq
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| sym::simd_ne
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| sym::simd_lt
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| sym::simd_le
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| sym::simd_gt
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| sym::simd_ge => (2, 0, vec![param(0), param(0)], param(1)),
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sym::simd_add
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| sym::simd_sub
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| sym::simd_mul
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| sym::simd_rem
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| sym::simd_div
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| sym::simd_shl
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| sym::simd_shr
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| sym::simd_and
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| sym::simd_or
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| sym::simd_xor
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| sym::simd_fmin
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| sym::simd_fmax
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| sym::simd_fpow
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| sym::simd_saturating_add
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| sym::simd_saturating_sub => (1, 0, vec![param(0), param(0)], param(0)),
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sym::simd_arith_offset => (2, 0, vec![param(0), param(1)], param(0)),
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sym::simd_neg
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| sym::simd_bswap
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| sym::simd_bitreverse
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| sym::simd_ctlz
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| sym::simd_cttz
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2024-05-18 17:56:49 -07:00
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| sym::simd_ctpop
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2024-02-23 18:26:39 +01:00
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| sym::simd_fsqrt
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| sym::simd_fsin
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| sym::simd_fcos
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| sym::simd_fexp
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| sym::simd_fexp2
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| sym::simd_flog2
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| sym::simd_flog10
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| sym::simd_flog
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| sym::simd_fabs
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| sym::simd_ceil
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| sym::simd_floor
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| sym::simd_round
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| sym::simd_trunc => (1, 0, vec![param(0)], param(0)),
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sym::simd_fpowi => (1, 0, vec![param(0), tcx.types.i32], param(0)),
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2024-11-23 14:31:20 -05:00
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sym::simd_fma | sym::simd_relaxed_fma => {
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(1, 0, vec![param(0), param(0), param(0)], param(0))
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}
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2024-02-23 18:26:39 +01:00
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sym::simd_gather => (3, 0, vec![param(0), param(1), param(2)], param(0)),
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sym::simd_masked_load => (3, 0, vec![param(0), param(1), param(2)], param(2)),
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2024-05-02 17:49:23 +02:00
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sym::simd_masked_store => (3, 0, vec![param(0), param(1), param(2)], tcx.types.unit),
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sym::simd_scatter => (3, 0, vec![param(0), param(1), param(2)], tcx.types.unit),
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2024-02-23 18:26:39 +01:00
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sym::simd_insert => (2, 0, vec![param(0), tcx.types.u32, param(1)], param(0)),
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sym::simd_extract => (2, 0, vec![param(0), tcx.types.u32], param(1)),
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sym::simd_cast
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| sym::simd_as
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| sym::simd_cast_ptr
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2024-04-03 15:17:00 +02:00
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| sym::simd_expose_provenance
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2024-03-23 23:00:53 +01:00
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| sym::simd_with_exposed_provenance => (2, 0, vec![param(0)], param(1)),
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2024-02-23 18:26:39 +01:00
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sym::simd_bitmask => (2, 0, vec![param(0)], param(1)),
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sym::simd_select | sym::simd_select_bitmask => {
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(2, 0, vec![param(0), param(1), param(1)], param(1))
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}
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sym::simd_reduce_all | sym::simd_reduce_any => (1, 0, vec![param(0)], tcx.types.bool),
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sym::simd_reduce_add_ordered | sym::simd_reduce_mul_ordered => {
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(2, 0, vec![param(0), param(1)], param(1))
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}
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sym::simd_reduce_add_unordered
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| sym::simd_reduce_mul_unordered
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| sym::simd_reduce_and
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| sym::simd_reduce_or
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| sym::simd_reduce_xor
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| sym::simd_reduce_min
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| sym::simd_reduce_max => (2, 0, vec![param(0)], param(1)),
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sym::simd_shuffle => (3, 0, vec![param(0), param(0), param(1)], param(2)),
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sym::simd_shuffle_generic => (2, 1, vec![param(0), param(0)], param(1)),
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2020-06-28 12:58:20 +02:00
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other => {
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2024-01-31 14:09:42 +00:00
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tcx.dcx().emit_err(UnrecognizedIntrinsicFunction { span, name: other });
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2015-08-06 11:29:26 -07:00
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return;
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}
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};
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2024-05-17 14:17:48 -03:00
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(n_tps, 0, n_cts, inputs, output, safety)
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2015-08-06 11:29:26 -07:00
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};
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2024-05-17 14:17:48 -03:00
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let sig = tcx.mk_fn_sig(inputs, output, false, safety, abi);
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2020-10-26 14:18:31 -04:00
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let sig = ty::Binder::bind_with_vars(sig, bound_vars);
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2024-01-31 14:22:10 +00:00
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equate_intrinsic_type(tcx, span, intrinsic_id, n_tps, n_lts, n_cts, sig)
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2015-08-06 11:29:26 -07:00
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}
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