Merge commit '3270432f4b' into sync_cg_clif-2024-05-13
This commit is contained in:
bjorn3
commit
75f8bdbca4
31 changed files with 481 additions and 166 deletions
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@ -127,7 +127,7 @@ pub(crate) fn codegen_inline_asm_terminator<'tcx>(
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}
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InlineAsmOperand::SymStatic { def_id } => {
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assert!(fx.tcx.is_static(def_id));
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let instance = Instance::mono(fx.tcx, def_id).polymorphize(fx.tcx);
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let instance = Instance::mono(fx.tcx, def_id);
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CInlineAsmOperand::Symbol { symbol: fx.tcx.symbol_name(instance).name.to_owned() }
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}
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InlineAsmOperand::Label { .. } => {
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@ -169,6 +169,7 @@ pub(crate) fn codegen_inline_asm_inner<'tcx>(
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stack_slots_input: Vec::new(),
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stack_slots_output: Vec::new(),
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stack_slot_size: Size::from_bytes(0),
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is_naked: false,
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};
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asm_gen.allocate_registers();
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asm_gen.allocate_stack_slots();
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@ -209,6 +210,121 @@ pub(crate) fn codegen_inline_asm_inner<'tcx>(
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call_inline_asm(fx, &asm_name, asm_gen.stack_slot_size, inputs, outputs);
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}
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pub(crate) fn codegen_naked_asm<'tcx>(
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tcx: TyCtxt<'tcx>,
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cx: &mut crate::CodegenCx,
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module: &mut dyn Module,
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instance: Instance<'tcx>,
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span: Span,
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symbol_name: &str,
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template: &[InlineAsmTemplatePiece],
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operands: &[InlineAsmOperand<'tcx>],
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options: InlineAsmOptions,
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) {
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// FIXME add .eh_frame unwind info directives
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let operands = operands
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.iter()
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.map(|operand| match *operand {
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InlineAsmOperand::In { .. }
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| InlineAsmOperand::Out { .. }
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| InlineAsmOperand::InOut { .. } => {
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span_bug!(span, "invalid operand type for naked asm")
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}
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InlineAsmOperand::Const { ref value } => {
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let cv = instance.instantiate_mir_and_normalize_erasing_regions(
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tcx,
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ty::ParamEnv::reveal_all(),
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ty::EarlyBinder::bind(value.const_),
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);
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let const_value = cv
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.eval(tcx, ty::ParamEnv::reveal_all(), value.span)
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.expect("erroneous constant missed by mono item collection");
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let value = rustc_codegen_ssa::common::asm_const_to_str(
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tcx,
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span,
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const_value,
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RevealAllLayoutCx(tcx).layout_of(cv.ty()),
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);
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CInlineAsmOperand::Const { value }
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}
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InlineAsmOperand::SymFn { ref value } => {
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if cfg!(not(feature = "inline_asm_sym")) {
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tcx.dcx()
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.span_err(span, "asm! and global_asm! sym operands are not yet supported");
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}
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let const_ = instance.instantiate_mir_and_normalize_erasing_regions(
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tcx,
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ty::ParamEnv::reveal_all(),
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ty::EarlyBinder::bind(value.const_),
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);
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if let ty::FnDef(def_id, args) = *const_.ty().kind() {
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let instance = ty::Instance::resolve_for_fn_ptr(
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tcx,
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ty::ParamEnv::reveal_all(),
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def_id,
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args,
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)
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.unwrap();
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let symbol = tcx.symbol_name(instance);
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// Pass a wrapper rather than the function itself as the function itself may not
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// be exported from the main codegen unit and may thus be unreachable from the
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// object file created by an external assembler.
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let inline_asm_index = cx.inline_asm_index.get();
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cx.inline_asm_index.set(inline_asm_index + 1);
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let wrapper_name = format!(
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"__inline_asm_{}_wrapper_n{}",
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cx.cgu_name.as_str().replace('.', "__").replace('-', "_"),
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inline_asm_index
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);
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let sig =
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get_function_sig(tcx, module.target_config().default_call_conv, instance);
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create_wrapper_function(
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module,
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&mut cx.unwind_context,
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sig,
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&wrapper_name,
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symbol.name,
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);
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CInlineAsmOperand::Symbol { symbol: wrapper_name }
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} else {
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span_bug!(span, "invalid type for asm sym (fn)");
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}
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}
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InlineAsmOperand::SymStatic { def_id } => {
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assert!(tcx.is_static(def_id));
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let instance = Instance::mono(tcx, def_id);
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CInlineAsmOperand::Symbol { symbol: tcx.symbol_name(instance).name.to_owned() }
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}
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InlineAsmOperand::Label { .. } => {
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span_bug!(span, "asm! label operands are not yet supported");
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}
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})
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.collect::<Vec<_>>();
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let asm_gen = InlineAssemblyGenerator {
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tcx,
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arch: tcx.sess.asm_arch.unwrap(),
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enclosing_def_id: instance.def_id(),
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template,
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operands: &operands,
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options,
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registers: Vec::new(),
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stack_slots_clobber: Vec::new(),
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stack_slots_input: Vec::new(),
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stack_slots_output: Vec::new(),
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stack_slot_size: Size::from_bytes(0),
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is_naked: true,
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};
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let generated_asm = asm_gen.generate_asm_wrapper(symbol_name);
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cx.global_asm.push_str(&generated_asm);
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}
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struct InlineAssemblyGenerator<'a, 'tcx> {
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tcx: TyCtxt<'tcx>,
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arch: InlineAsmArch,
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@ -221,10 +337,13 @@ struct InlineAssemblyGenerator<'a, 'tcx> {
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stack_slots_input: Vec<Option<Size>>,
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stack_slots_output: Vec<Option<Size>>,
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stack_slot_size: Size,
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is_naked: bool,
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}
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impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> {
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fn allocate_registers(&mut self) {
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assert!(!self.is_naked);
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let sess = self.tcx.sess;
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let map = allocatable_registers(
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self.arch,
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@ -348,6 +467,8 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> {
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}
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fn allocate_stack_slots(&mut self) {
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assert!(!self.is_naked);
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let mut slot_size = Size::from_bytes(0);
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let mut slots_clobber = vec![None; self.operands.len()];
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let mut slots_input = vec![None; self.operands.len()];
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@ -468,30 +589,32 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> {
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if is_x86 {
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generated_asm.push_str(".intel_syntax noprefix\n");
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}
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Self::prologue(&mut generated_asm, self.arch);
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if !self.is_naked {
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Self::prologue(&mut generated_asm, self.arch);
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// Save clobbered registers
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if !self.options.contains(InlineAsmOptions::NORETURN) {
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// Save clobbered registers
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if !self.options.contains(InlineAsmOptions::NORETURN) {
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for (reg, slot) in self
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.registers
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.iter()
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.zip(self.stack_slots_clobber.iter().copied())
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.filter_map(|(r, s)| r.zip(s))
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{
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Self::save_register(&mut generated_asm, self.arch, reg, slot);
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}
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}
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// Write input registers
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for (reg, slot) in self
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.registers
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.iter()
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.zip(self.stack_slots_clobber.iter().copied())
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.zip(self.stack_slots_input.iter().copied())
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.filter_map(|(r, s)| r.zip(s))
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{
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Self::save_register(&mut generated_asm, self.arch, reg, slot);
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Self::restore_register(&mut generated_asm, self.arch, reg, slot);
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}
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}
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// Write input registers
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for (reg, slot) in self
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.registers
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.iter()
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.zip(self.stack_slots_input.iter().copied())
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.filter_map(|(r, s)| r.zip(s))
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{
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Self::restore_register(&mut generated_asm, self.arch, reg, slot);
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}
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if is_x86 && self.options.contains(InlineAsmOptions::ATT_SYNTAX) {
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generated_asm.push_str(".att_syntax\n");
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}
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@ -553,30 +676,32 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> {
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generated_asm.push_str(".intel_syntax noprefix\n");
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}
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if !self.options.contains(InlineAsmOptions::NORETURN) {
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// Read output registers
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for (reg, slot) in self
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.registers
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.iter()
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.zip(self.stack_slots_output.iter().copied())
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.filter_map(|(r, s)| r.zip(s))
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{
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Self::save_register(&mut generated_asm, self.arch, reg, slot);
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}
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if !self.is_naked {
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if !self.options.contains(InlineAsmOptions::NORETURN) {
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// Read output registers
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for (reg, slot) in self
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.registers
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.iter()
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.zip(self.stack_slots_output.iter().copied())
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.filter_map(|(r, s)| r.zip(s))
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{
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Self::save_register(&mut generated_asm, self.arch, reg, slot);
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}
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// Restore clobbered registers
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for (reg, slot) in self
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.registers
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.iter()
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.zip(self.stack_slots_clobber.iter().copied())
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.filter_map(|(r, s)| r.zip(s))
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{
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Self::restore_register(&mut generated_asm, self.arch, reg, slot);
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}
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// Restore clobbered registers
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for (reg, slot) in self
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.registers
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.iter()
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.zip(self.stack_slots_clobber.iter().copied())
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.filter_map(|(r, s)| r.zip(s))
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{
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Self::restore_register(&mut generated_asm, self.arch, reg, slot);
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}
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Self::epilogue(&mut generated_asm, self.arch);
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} else {
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Self::epilogue_noreturn(&mut generated_asm, self.arch);
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Self::epilogue(&mut generated_asm, self.arch);
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} else {
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Self::epilogue_noreturn(&mut generated_asm, self.arch);
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}
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}
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if is_x86 {
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